Determining and analyzing integrated circuit yield and quality

ABSTRACT

Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication No. 60/607,728 filed on Sep. 6, 2004, which is herebyincorporated herein by reference.

TECHNICAL FIELD

The disclosed technology relates generally to the design and testing ofintegrated circuits.

BACKGROUND

As feature sizes of integrated circuits continue to decrease, theeffects of feature-related defects are becoming increasingly important.For example, the lithographic techniques used to realize today'sintegrated circuit often use light having a wavelength that is largerthan the features it creates. One consequence of sub-wavelengthlithography is that failures caused by the lithography process (forexample, distortion that causes shorts and opens to appear in theresulting design) become more numerous. Indeed, the effect of featuredefects on the production yield of integrated circuits is increasing andhas become more dominant than the effect of random particles presentduring fabrication.

To reduce the number of defective chips being produced, foundries(integrated circuit manufacturers) often provide a number of recommendeddesign rules that designers can use to help improve the yield of theirparticular design. Such rules are generally referred to herein as Designfor Manufacturability (DFM) rules and can pertain to a wide variety ofparameters related to integrated circuit design. For example, the rulecould pertain to a physical characteristic or trait of the design, suchas a distance between two wires or between corners of two features.Among the possible design issues addressed by DFM rules are: redundancy,spacing, width, length, area, enclosure, extension, overlap, density,orientation, job/notch, antenna, and matching. Further, each of thesecategories can have numerous rules that apply. Further, a foundry canprovide multiple rules for a given design parameter, each having adifferent potential effect on yield. For instance, a foundry can providea minimum or maximum value for a particular parameter as well as arecommended value. In general, the use of DFM rules helps ensure thatthe integrated circuit is actually manufacturable using the process andtechnology implied by the DFM rules.

DFM rules have been traditionally determined through the use of testchips. A test chip is a specialized chip comprising numerous groups ofidentical test structures that systematically vary across some parameterbeing targeted for a particular DFM rule. Test results obtained from thetest chips can then be statistically analyzed and used to determine thevalues for the targeted DFM rules. Test chips, however, can be expensiveto use—both in terms of actual cost and in terms of the lost wafercapacity resulting from the creation, testing, and analyzing of the testchips. Test chips also provide limited information. For example, testchips cannot ordinarily provide information on the impact of features ofa circuit not contained in a test structure of the test chip. Further,as new DFM rules are developed to address process changes or newknowledge obtained, new test chips must be designed and manufactured—aprocess that commonly takes weeks to months.

Accordingly, improved methods of determining, modifying, and usingdesign manufacturing rules to increase yield are desired.

SUMMARY

Disclosed below are representative embodiments of methods, apparatus,and systems that should not be construed as limiting in any way.Instead, the present disclosure is directed toward all novel andnonobvious features and aspects of the various disclosed methods,apparatus, systems, and equivalents thereof, alone and in variouscombinations and subcombinations with one another.

In one of the exemplary methods disclosed herein, a set of design defectextraction rules is derived at least partially from a set of designmanufacturing rules. Potential defects are extracted from arepresentation of a physical-layout of an integrated circuit design,wherein the extracted potential defects are based at least in part uponthe defect extraction rules. Circuit test stimuli applied during one ormore circuit tests are determined. Test responses resulting from theapplied circuit tests are evaluated to identify integrated circuits thatfail and to identify the occurrence in the failing integrated circuitsof one or more potential types of defects associated with the appliedcircuit tests. Information is collected concerning the repetitiveidentification in the failing integrated circuits of the occurrence ofpotential types of defects. The collected information is analyzed todetermine the likelihood of potential types of defects being present inintegrated circuits manufactured in accordance with the physical layout.The circuit test stimuli can comprise test patterns generated bytargeting one or more of the extracted potential defects and/orpreviously generated test patterns that are determined to detect one ormore of the extracted potential defects. One or more of the extracteddefects can additionally have at least one of the following propertiesassociated with it: (a) a defect identifier that distinguishes arespective potential defect from other potential defects; (b) a derivedrule identifier that identifies the defect extraction rule used toextract the respective potential defect; (c) a design manufacturing ruleidentifier that identifies the design manufacturing rule from which thedefect extraction rule used to extract the respective potential defectwas derived; (d) one or more physical properties of the respectivepotential defect in the physical layout of the integrated circuitdesign; (e) a physical location of the respective potential defect inthe physical layout of the integrated circuit design; and (f) a rankingof the respective potential defect relative to other potential defects.In certain embodiments, a ranking is assigned to at least some of theextracted potential defects, wherein the ranking is indicative of thelikelihood of a potential defect occurring in the integrated circuit.This ranking can be updated based at least in part upon the analysis ofthe collected information. Further, the application of the circuit testscan be ordered based at least in part upon the extracted potentialdefects and the ranking of the extracted potential defects. In someembodiments, the act of analyzing the collected information furthercomprises analyzing collected information for a multiplicity of testedintegrated circuits and performing one or more of the following acts:(a) estimating the production yield of the integrated circuits; (b)estimating an escape rate of potential types of defects or integratedcircuits manufactured in accordance with the physical layout of theintegrated circuit design; (c) estimating a yield sensitivity curve forone or more of the design manufacturing rules; (d) estimating theproduction yield of other integrated circuits designs using at least aplurality of the design defect extraction rules; (e) estimating theescape rate of potential types of defects in other integrated circuitdesigns designed in accordance with the design manufacturing rules. Incertain embodiments, the act of analyzing the collected informationfurther comprises analyzing collected information for a multiplicity oftested integrated circuits over time and determining trends in changesin the likelihood of potential defects being present in manufacturedintegrated circuits. Based at least in part on the determined trends,test stimuli can be modified, added, or deleted in order to improve thelikelihood of identifying defective integrated circuits. In someembodiments, the acts of collecting information and analyzing thecollected information are performed substantially in real time onmanufactured integrated circuits being produced in a production line ofan integrated circuit fabricator. In exemplary embodiments of thedisclosed technology, test responses and the associated test thatproduced such test responses are compared using a previously generatedand stored dictionary of failing test responses expected from a failureof the associated test. In these embodiments, the act of collectinginformation can further comprise collecting information from thecomparison that identifies the potential defects identified by thecomparison. In some embodiments, the information stored in thedictionary is compressed during generation of the dictionary. Forexample, one or more bit masks can be computed to represent thedetecting test responses for at least one potential defect in theintegrated circuit design, or one or more pseudo faults can be computedto represent the detecting test responses for at least one potentialdefect in the integrated circuit design. Some embodiments furthercomprise modifying the dictionary in one or more of the followingmanners: (a) adding at least one test associated with the potentialdefect not previously found in the dictionary; or (b) adding at leastone expected failing test response expected to be received in the eventthe potential defect not previously found in the generated dictionary ispresent in a tested integrated circuit. An entry of the generateddictionary can also be deleted (for example, when a failing testresponse associated with the entry has not been observed for a thresholdnumber of circuit tests). In some embodiments of the disclosed method,the existence of at least one potential defect not found in thegenerated dictionary can also be diagnosed (for example, usingincremental diagnosis or incremental simulation). Design manufacturingrules in the set of design manufacturing rules or design defectextraction rules can be modified, added, or deleted based at least inpart upon the act of analyzing the collected information.

In another one of the exemplary methods disclosed herein, arepresentation of an integrated circuit layout is received (for example,a GDSII or Oasis file). One or more recommended design parameters formanufacturing an integrated circuit are also received. Extraction rulesfrom one or more of the recommended design parameters are determined,wherein the extraction rules comprise rules for identifying two or moresets of defect candidates from the representation of the integratedcircuit layout. The design parameters can comprise, for example, one ormore design manufacturing rules. Further, the two or more sets of defectcandidates can comprise defect candidates that deviate from anassociated recommended design parameter by different respective rangesof values. In some embodiments, the extraction rules are modified basedat least in part on test results obtained from testing integratedcircuits produced according to the integrated circuit layout. Themodification can comprise, for example, an increase in the number ofsets of defect candidates identified by the extraction rules. Theextraction rules can be applied to the representation of the integratedcircuit layout to generate a list of defect candidates in the integratedcircuit layout. Test patterns can be generated that target at least someof the defect candidates. Alternatively, or additionally, test patternscan be identified from a set of previously generated test patterns thatdetect at least some of the defect candidates. In some embodiments, thelist of defect candidates is ordered based at least in part on a yieldsensitivity associated with one or more of the defect candidates. Incertain embodiments of the exemplary method, a fault dictionaryindicative of failing test responses and associated defect candidatesthat potentially caused the failing test response is generated.

In another exemplary method disclosed herein, a modified set of designmanufacturing rules for evaluating the presence of potential defects inmanufactured integrated circuits is determined. The modified set ofdesign manufacturing rules is derived at least in part from a first setof design manufacturing rules, wherein the first set of designmanufacturing rules defines plural classes of types of potentialdefects, including at least first and second classes of defect types. Inthis embodiment, the modified set of design manufacturing rules definesat least a first set of a first subclass of plural design manufacturingrules associated with the first class of design manufacturing rules anda second set of a second subclass of plural design manufacturing rulesassociated with the second class of design manufacturing rules. At leasta plurality of the first and second subclasses of design manufacturingrules are ranked by the likelihood of such ranked first and secondsubclasses of design manufacturing rules identifying defects in themanufactured integrated circuits. Potential defects are extracted from aphysical layout description of the integrated circuit that satisfy thefirst and second subclasses of design manufacturing rules. In certainembodiments of the method, circuit tests to be applied to manufacturedcircuits are determined. The circuit tests can be configured, forexample, to detect extracted potential defects associated with at leasta plurality of the design manufacturing rules included in the first andsecond subclasses of design manufacturing rules. Test responses from themanufactured circuits obtained in response to the circuit tests beingapplied can be evaluated to determine whether one or more of themodified design manufacturing rules has identified potential defectslikely to be present in the tested integrated circuits. Further, theevaluation can be performed using tests responses from a sufficientnumber of manufactured integrated circuits to provide statisticalinformation indicating the likelihood of the occurrence in amanufactured circuit of defects detected by the applied circuit tests.In certain embodiments, the act of ranking the first and secondsubclasses of design manufacturing rules comprises ranking plural designmanufacturing rules in the first subclass relative to one another andranking plural design manufacturing rules in the second subclassrelative to one another. In some embodiments, the modified set of designmanufacturing rules comprises design manufacturing rules defining areasof a physical layout of an integrated circuit for which no defects areto be extracted. The modified set of design manufacturing rules can alsocomprise yield loss limiting manufacturing rules for determining trendsin changes in yield loss impacting characteristics over time. An exampleof one such yield loss limiting rule relates to the in-line resistanceof signal lines.

In another exemplary method disclosed herein, one or more faultdictionaries are generated for identifying one or more defect candidatesfrom corresponding observation point combinations. In this exemplarymethod, the observation point combinations indicate the observationpoints of a circuit-under-test that captured faulty test values uponapplication of a respective test pattern. Further, the one or more faultdictionary are generated by: (a) for a first defect candidate, storingone or more first indicators indicative of test patterns detecting thefirst defect candidate, and (b) for a second defect candidate, storingat least a second indicator indicative of the test patterns that detectthe second defect candidate, the second indicator-comprising a bit maskthat indicates which of the test patterns detecting the first defectcandidate also detect the second defect candidate. In some embodiments,the circuits-under-test comprise integrated circuits designed forfunctional use in electronic devices. The one or more first indicatorscan comprise unique IDs associated with the test patterns detecting thefirst defect candidate and/or unique IDs associated with the observationpoint combinations for the test patterns detecting the first defectcandidate. In some embodiments, the first defect candidate and thesecond defect candidate are in a fan-out free region of thecircuit-under-test. Further, the first defect candidate can be locatedat a stem of the fan-out free region. In some embodiments, one or moredefect candidates are identified during production testing of thecircuits-under-test using the generated one or more fault dictionaries.Further, in certain embodiments, incremental diagnosis and/orincremental simulation is performed on one or more possible defects notidentified by the generated one or more fault dictionaries. In someembodiments, the generated one or more fault dictionaries are updatedwith results from the incremental diagnosis and/or incrementalsimulation. Similarly, defect extraction rules or design manufacturingrules can be updated with results from the incremental diagnosis and/orincremental simulation. The number of test patterns detecting the firstdefect candidate can be limited to at least one of the following: (a) apredetermined value; or (b) a user-selected value. In some embodiments,the test patterns detecting the first defect candidate comprise testpatterns using static fault models and test patterns using dynamic faultmodels. Further, in certain implementations of these embodiments, atleast a first fault dictionary and a second fault dictionary aregenerated, and the fault dictionary information concerning the testpatterns using static fault model are stored in the first faultdictionary whereas fault dictionary information concerning the testpatterns using dynamic fault models is stored in the second faultdictionary. Further, at least some of the test patterns detecting thesecond defect candidate can use a different type of fault model thanused to detect the first defect candidate. In some embodiments of theexemplary method, the observation point combinations correspond tocompacted test responses output from a compactor in thecircuit-under-test. In some embodiments, one or more of the followingproperties are associated with or additionally stored for at least thefirst defect candidate: (a) a defect identifier that distinguishes thedefect candidate from other potential defects; (a derived ruleidentifier that identifies the defect extraction rule used to extractthe first defect candidate; (c) a design manufacturing rule identifierthat identifies the design manufacturing rule from which the defectextraction rule used to extract the first defect candidate was derived;(d) one or more physical properties of the first defect candidate; (e) aphysical location of the first defect candidate in the physical layoutof the integrated circuit design; or (f) a ranking of the first defectcandidate relative to other potential defects of the same type.

In another exemplary method disclosed herein, a list of potentialdefects in an integrated circuit layout is received. In this exemplaryembodiment, the potential defects in the list were identified by usingextraction rules derived at least partially from a set of designmanufacturing rules, the design manufacturing rules comprising designparameters for manufacturing an integrated circuit. A set of testpatterns is produced by: (a) selecting from previously generated testpatterns one or more test patterns that detect at least some of theidentified potential defects; (b) generating one or more test patternsthat explicitly target at least some of the identified potentialdefects; or both (a) and (b). At least one fault dictionary isgenerated, wherein the fault dictionary is indicative of one or morefailing test responses to an associated test pattern and one or morepotential defects respectively associated with the failing testresponses. In certain embodiments, the at least one fault dictionary isa compressed fault dictionary and the act of generating the dictionarycomprises using one or more bit masks to represent the failing testresponses associated with a respective potential defect and/or usingdetection information of one or more pseudo faults to represent thedetection information of a respective potential defect. Test-result datacan be received that comprises failing test responses obtained duringtesting of the integrated circuits using at least a portion of the testpatterns in the set of test patterns. The at least one fault dictionarycan be applied to the test-result data in order to diagnose potentialdefects associated with one or more of the failing test responses. Anincremental diagnosis or incremental simulation procedure can be used todiagnose potential defects that are not diagnosable using the at leastone fault dictionary. Probabilities that potential defects are actuallycausing the failing test responses can be statistically determined usingdiagnostic results obtained from the application of the at least onefault dictionary.

In another exemplary embodiment disclosed herein, a set of defectextraction rules at least partially derived from a first set of designmanufacturing rules is determined. The defect extraction rules define,for example, plural subcategories of at least one category of potentialdefects identified by the design manufacturing rules. Potential defectsare extracted by applying at least a subset of the defect extractionrules to an electronic description of the physical layout of anintegrated circuit. The extracted potential defects of this exemplaryembodiment fall into at least one of the subcategories. Plural circuittests are defined that indicate the presence of potential defects in themanufactured integrated circuits. The circuit tests each comprise, forexample, a set of circuit stimuli to be applied to manufacturedintegrated circuits containing the integrated circuit. For at least aplurality of circuit tests, the potential defect or defects detected bythe circuit test and the failing test responses that, if observed, wouldindicate the presence of the potential defect or defects detected by thecircuit test are stored. The method can further comprise applying thecircuit tests to the manufactured integrated circuits, capturing testresponses, and determining failing integrated circuits that produce oneor more test responses that fail the applied circuit tests. In certainembodiments, for one or more of the failing integrated circuits, one ormore circuit tests are identified that produced the failing testresponse or responses, and one or more of the failing test responsesassociated with an identified circuit test are compared with storedfailing test responses associated with the identified circuit test tothereby attempt to deduce one or more defects that potentially causedthe failing test response. The amount of data stored when storing theresults of such comparison can be compressed or limited by at least, foreach potential defect, only storing k detecting failing test responses,wherein k designates the maximum number of failing test responses forthe potential defect that are stored. Some embodiments of the exemplarymethod further comprise collecting and analyzing information concerningthe repetitive identification of the occurrence of potential types ofdefects in the failing integrated circuits, and reporting datarepresenting the probability that certain types of defects are causingthe failing test responses. The reporting can be performed, for example,by generating a graphical representation of the data (for example, apareto chart). In some embodiments, one or more of the followingproperties associated with a respective potential defect can also bestored: (a) a defect identifier that distinguishes the respectivepotential defect from other potential defects; (b) a derived ruleidentifier that identifies the defect extraction rule used to extractthe potential defect; (c) a design manufacturing rule identifier thatidentifies the design manufacturing rule on which the defect extractionrule is based; (d) one or more physical properties of the respectivepotential defect in the physical layout of the integrated circuitdesign; (e) the physical location of the respective potential defect inthe physical layout of the integrated circuit design; and (f) a rankingof the respective potential defect relative to other potential defects.In certain embodiments, the set of defect extraction rules alsocomprises at least one potential defect identified by a worst casedefect identifier as a worst case defect. In some embodiments, the actof storing comprises the act of generating a defect comparisondictionary describing failing test-responses by an identification of thepotential defect the fault was derived from, the type of potentialfault, the test patterns detecting the potential fault, and theobservation points for each detecting test pattern. Further, in someimplementations of these embodiments, the exemplary method furthercomprises modifying the stored information by performing one or more ofthe following: (a) adding a potential defect not previous found in thedictionary; (b) adding at least one test associated with the potentialdefect not previously found in the dictionary; (c) adding at least oneexpected failing test response expected to be received in the event thepotential defect not previously found in the dictionary is present in atested integrated circuit, or (d) deleting an entry in the dictionaryassociated with a test response that has not detected a failing circuitafter a predetermined or user-selected number of circuit tests. Also, incertain implementations that use a defect comparison dictionary, failingtest responses associated with one of the circuit tests are comparedwith failing test responses associated with the circuit test stored inthe dictionary to determine the existence of potential defects and thetypes of such defects; and the results of such comparison are stored. Aspart of this process, integrated circuits that fail due to miscellaneouspotential defects not identified by the comparison can be identified andthe exemplary method can be repeated using a modified set of defectextraction rules to target at least one of the miscellaneous potentialdefects. Further, in certain implementations, the miscellaneouspotential defect not identified by the comparison can be diagnosed toidentify the miscellaneous potential defect (for example, using aneffect-cause-based diagnosis procedure, incremental simulation and/orincremental diagnosis). The dictionary can be modified to include theidentified miscellaneous potential defect.

In another one of the exemplary methods disclosed, test-resultinformation is received from tests of multiple integrated circuits. Thetest-result information comprises failing test responses associated withrespective test patterns applied during the tests. A fault dictionary isused to diagnose at least a portion of the test-result information inorder to identify potential defects that may have caused one or more ofthe failing test responses. At least one of an incremental diagnosis orincremental simulation procedure is used to diagnose test-resultinformation that was not diagnosable using the fault dictionary. In someembodiments, probabilities that one or more of the potential defectsactually caused the integrated circuit failures are determined fromdiagnostic results produced using the fault dictionary. Theseprobabilities are then reported. One or more of the following acts canbe performed based at least in part on the reported probabilities: (a)adjusting one or more design manufacturing rules; (b) adjusting one ormore defect extraction rules; or (c) providing recommended modificationsof one or more features in the integrated circuit. In some embodiments,the fault dictionary is a compressed fault dictionary using one or morebit masks to associate one or more failing test responses to respectivepotential defects.

In another exemplary method disclosed herein, information is receivedfrom processing test responses of integrated circuits designed forfunctional use in electronic devices. In this embodiment, theinformation is indicative of integrated circuit failures observed duringtesting of the integrated circuits and of possible yield limitingfactors. causing the integrated circuit failures. Probabilities that oneor more of the possible yield limiting factors in the integratedcircuits actually caused the integrated circuit failures are determinedby statistically analyzing the received information. The probabilitiesthat one or more possible yield limiting factors actually caused theintegrated circuit failures are reported. The information received cancomprise, for example, one or more of the following: (a) diagnosisresults; (b) one or more lists of yield limiting factors; or (c)information about detection of the yield limiting factors during thetesting. In some embodiments, an estimate of the yield of the integratedcircuits is determined based at least in part on the determinedprobabilities. A yield estimation can also be determined for otherintegrated circuits. In certain embodiments, an estimate of the escaperate of a respective possible yield limiting factor or of the integratedcircuits is determined based at least in part on the determinedprobabilities. An escape rate estimation of possible yield limitingfactors in other integrated circuits or of the other integrated circuitscan also be determined, wherein the other integrated circuits aredesigned in accordance with design manufacturing rules substantiallysimilar to design manufacturing rules used to design the testedintegrated circuits. In some embodiments, the tested integrated circuitsare designed in accordance with one or more design manufacturing rules,and the exemplary method further comprises estimating a yieldsensitivity curve for at least one of the design manufacturing rules,wherein the estimation is based at least in part on the determinedprobabilities. Further, the exemplary method can be performedrepetitively over time, and can comprise determining production trendsbased on changes in the determined probabilities observed over time.Based at least in part on the reported probabilities: (a) one or moredesign manufacturing rules can be modified, (b) one or more defectextraction rules used to identify potential defects in a design of theintegrated circuits can be modified; and/or (c) one or more recommendedmodifications to features in the integrated circuits can be provided(and, in some instances, integrated circuits having the modifiedfeatures produced). In some embodiments, a graphical representation ofthe probabilities is generated (for example, a pareto chart). In certainembodiments, the received information comprises a list of suspectfeatures. The list of suspect features can be generated, for example,using at least one compressed fault dictionary and/or incrementaldiagnosis. In some embodiments, the probabilities are determined byestimating a probability that a respective possible yield limitingfactor caused an associated respective integrated circuit failure, anditeratively solving a system of equations relating the estimatedprobability to an actual probability that the respective possible yieldlimiting factor caused the associated failure. Further, in certainembodiments, the possible yield limiting factors comprise at least oneof: (a) nets in the integrated circuit layout, (b) features in theintegrated circuit layout, or (c) design manufacturing rules associatedwith the manufacture of the integrated circuit. Moreover, the integratedcircuits tested can have a common design, and the act of determining theprobabilities can comprise partitioning the design of the integratedcircuits into multiple design blocks, wherein each design blockcomprising a subset of the possible yield limiting factors. Thispartitioning procedure can comprise simulating faults associated withnets in the design of the integrated circuits, identifying at least afirst group of observation points that captures errors from a first setof nets and a second group of observation points that captures errorsfrom a second set of nets, and including the first set of nets in afirst design block and the second set of nets in a second design block.The act of determining the probabilities can further compriseconstructing probability models relating design block fail probabilitiesto fail probabilities of yield limiting factors contain in respectivedesign blocks, comparing the design block fail probabilities to thereceived information; and computing estimated fail probabilities ofyield limiting factors using regression techniques. The act ofdetermining the probabilities can also comprise identifying nets thatfail at a substantially higher rate than other nets. A determination canbe made whether the nets that fail at a substantially higher rate thanother nets occur repetitively at or near a same die location of multiplewafers containing multiples instances of dies that each contain aninstance of the tested integrated circuit (for example, by generating awafer defect map). In some embodiments of the exemplary method, thetesting of the multiple integrated circuits includes identifyingpotential defects in the integrated circuits using a fault dictionary inwhich one or more potential defects are identified by applying a bitmask.

In yet another exemplary embodiment disclosed herein, information fromprocessing test responses of integrated circuits is received. In thisembodiment, the information is indicative of integrated circuit failuresobserved during testing of the integrated circuits and potential defectsthat may have caused the integrated circuit failures. Probabilities thatthe potential defects are actually causing the integrated circuitfailures are determined by analyzing the received information. In thisembodiment, the act of includes iteratively solving a system ofequations relating an estimated probability to an actual probabilitythat a respective potential defect caused the associated integratedcircuit failure. The determined probabilities can be reported (forexample, by generating a graphical representation of the probabilities,such as a pareto chart). The information received can comprise, forexample, one or more of the following: (a) diagnosis results; (b) one ormore lists of the potential defects; or (c) information about detectionof the potential defects during the testing. In some embodiments, anestimate of the yield of the integrated circuits is determined based atleast in part on the determined probabilities. A yield estimation canalso be determined for other integrated circuits. In certainembodiments, an estimate of the escape rate of a respective potentialdefect or of the integrated circuits is determined based at least inpart on the determined probabilities. An escape rate estimation ofpotential defects in other integrated circuits or of the otherintegrated circuits can also be determined. In some embodiments, thetested integrated circuits are designed in accordance with one or moredesign manufacturing rules, and the exemplary method further comprisesestimating a yield sensitivity curve for at least one of the designmanufacturing rule the estimation being based at least in part on thedetermined probabilities. Further, the exemplary method can be performedrepetitively over time, and can comprise determining production trendsbased on changes in the determined probabilities observed over time. Incertain embodiments, one or more of the following acts are performedbased at least in part on the reported probabilities: (a) adjusting oneor more design manufacturing rules; (b) adjusting one or more defectextraction rules; or (c) providing recommended modification for one ormore features in the integrated circuit. In implementations wherein oneor more features in the integrated circuit are modified based at leastin part on the reported probabilities, the exemplary method can furthercomprise producing one or more integrated circuits having the modifiedone or more features. In certain embodiments, the integrated circuitstested have a common design, and the act of determining theprobabilities comprises partitioning the design of the integratedcircuits into multiple design blocks and analyzing the design blocks asdescribed in the previous paragraph. For example, the partitioningprocedure can comprise simulating faults associated with nets in thedesign of the integrated circuits, identifying at least a first group ofobservation points that captures errors from a first set of nets and asecond group of observation points that captures errors from a secondset of nets, and including the first set of nets in a first design blockand the second set of nets in a second design block. The act ofdetermining the probabilities can further comprise constructingprobability models relating design block fail probabilities to failprobabilities of potential defects in respective design blocks,comparing the design block fail probabilities to the receivedinformation; and computing estimated fail probabilities of the potentialdefects using regression techniques. The act of determining theprobabilities can also comprise identifying nets that fail at asubstantially higher rate than other nets. A determination can be madewhether the nets that fail at a substantially higher rate than othernets occur repetitively at or near a same die location of multiplewafers containing multiples instances of dies that each contain aninstance of the tested integrated circuit (for example, by generating awafer defect map). In certain embodiments, the received information isfurther indicative of one or more of the following properties associatedwith a respective potential defect: (a) a defect identifier thatdistinguishes the respective potential defect from other potentialdefects; (b) a derived rule identifier that identifies the defectextraction rule used to extract the respective potential defect; (c) adesign manufacturing rule identifier that identifies the manufacturingrule that the defect extraction rules was based on; (d) one or morephysical properties of the respective potential defect; (e) a physicallocation of the respective potential defect in the physical layout ofthe integrated circuit design; and (f) a ranking of the respective,potential defect relative to other potential defects in the same classof potential defects.

In another exemplary embodiment disclosed herein, information isreceived that is indicative of integrated circuit failures observedduring testing of multiple integrated circuits and potential defectsthat may have caused the integrated circuit failures, the potentialdefects having been extracted and targeted for testing using extractionrules derived from design manufacturing rules. The information receivedis analyzed to determine one or more failure rates associated with oneor more of the potential defects, and the determined failure ratesreported. The information received can comprise, for example, one ormore of the following: (a) diagnosis results; (b) one or more lists ofthe potential defects; or (c) information about detection of thepotential defects during the testing. In some embodiments, an estimateof the yield of the integrated circuits is determined based at least inpart on the determined failure rates. A yield estimation can also bedetermined for other integrated circuits. In certain embodiments, anestimate of the escape rate of a respective potential defect or of theintegrated circuits is determined based at least in part on thedetermined failure rates. An escape rate estimation of potential defectsin other integrated circuits or of the other integrated circuits canalso be determined. In some embodiments, the exemplary method furthercomprises estimating a yield sensitivity curve for at least one of thedesign manufacturing rules, the estimation being based at least in parton the determined failure rates. Further, the exemplary method can beperformed over multiple time periods, and production trends can bedetermined based on changes in the determined failure rates observedover the multiple time periods. One of more of the following actions canbe performed based at least in part on the reported failure rates: (a)adjusting one or more design manufacturing rules; (b) adjusting one ormore defect extraction rules; or (c) providing recommended modificationsof one or more features in the integrated circuit. In implementationswherein one or more features in the integrated circuit are modifiedbased at least in part on the reported probabilities, the method canfurther comprise producing one or more integrated circuits having themodified one or more features. In certain embodiments, the diagnosticresults are obtained through application of at least one faultdictionary. For example, the at least one fault dictionary can be acompressed fault dictionary that uses one or more bit masks to identifypotential defects. In some embodiments, the act of analyzing comprisesconstructing probability models associated with the feature fail rates,relating the constructed probability models to the diagnostic resultsreceived, and computing estimated feature fail rates using regressionanalysis.

Any of the disclosed methods or procedures can be implemented intangible computer-readable media comprising computer-executableinstructions for causing a computer to perform the method. Further,tangible computer-readable media storing DFM rules created by any of thedescribed methods, a compressed fault dictionary for use with any of thedescribed methods, test patterns generated by any of the describedmethods, or results produced from, any of the described methods are alsodisclosed. Any of the disclosed methods can also be performed duringproduction testing of a circuit-under-test. Any of the disclosed methodsof procedures can also be performed by one or more computers programmedto perform the disclosed methods or procedures. Circuits having defectsidentified in part or design modified in part using any of the disclosedmethods are also considered to be within the scope of this disclosure.

The foregoing and additional features and advantages of the disclosedembodiments will become more apparent from the following detaileddescription, which proceeds with reference to the following drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the flow of an exemplary generalmethod for improving design manufacturing rules according to thedisclosed technology.

FIG. 2 is a block diagram illustrating a first DFM ruleexample—specifically, a rule stating that two signal lines must alwayskeep a minimum distance of d₁.

FIG. 3 is a block diagram illustrating a second DFM ruleexample—specifically, a rule stating that a signal line must always keepa minimum distance of d₂ from other layout features.

FIG. 4 is a block diagram showing an example of a connection of twosignal lines in different layers using a via.

FIGS. 5 and 6 are block diagrams showing examples of the location of avia connection on the end of a signal line.

FIGS. 7 and 8 are block diagrams showing examples of a connection of twosignal lines in different layers using a via.

FIG. 9 is a block diagram showing in greater detail an exemplary mannerin which component 13 of FIG. 1 can be performed.

FIG. 10 is a block diagram showing in greater detail an exemplary mannerin which component 13.1 of FIG. 9 can be performed.

FIG. 11 is a block diagram showing in greater detail an exemplary mannerin which component 13.2 of FIG. 9 can be performed.

FIG. 12 is a block diagram showing in greater detail an exemplary mannerin which component 13.2.1 of FIG. 11 can be performed.

FIG. 13 is a block diagram showing in greater detail a first exemplarymanner (13.2.2.A) in which component 13.2.2 of FIG. 11 can be performed.

FIG. 14 is a block diagram showing in greater detail a second exemplarymanner (13.2.2.B) in which component 13.2.2 of FIG. 11 can be performed.

FIG. 15 is a block diagram showing in greater detail a third exemplarymanner (13.2.2.C) in which component 13.2.2 of FIG. 11 can be performed.

FIG. 16 is a block diagram showing in greater detail an exemplary mannerin which component 13.2.3 of FIG. 11 can be performed.

FIG. 17 is a block diagram showing in greater detail an exemplary mannerin which component 13.3 of FIG. 9 can be performed.

FIG. 18 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.1 of FIG. 17 can be performed.

FIG. 19 is a block diagram showing in greater detail a first exemplarymanner in which component 13.3.1.1 of FIG. 18 can be performed.

FIG. 20 is a block diagram showing in greater detail a second exemplarymanner in which component 13.3.1.1 of FIG. 18 can be performed.

FIG. 21 is a block diagram showing in greater detail a third exemplarymanner in which component 13.3.1.1 of FIG. 18 can be performed.

FIG. 22 is a block diagram showing in greater-detail an exemplary mannerin which component 13.3.1.2 of FIG. 18 can be performed.

FIG. 23 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.1.3 of FIG. 18 can be performed.

FIG. 24 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.1.4 of FIG. 18 can be performed.

FIG. 25 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.1.5 of FIG. 18 can be performed.

FIG. 26 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.2 of FIG. 17 can be performed.

FIG. 27 is a block diagram showing in greater detail an exemplary mannerin which component 13.3.3 of FIG. 17 can be performed.

FIG. 28 is a block diagram illustrating an example of fault effectdifferences.

FIG. 29 is a block diagram illustrating a possible output responsecompaction problem in connection with the fault-effect differences ofFIG. 28.

FIG. 30 is a block diagram illustrating an output response compactionselection circuit.

FIG. 31 is a block diagram illustrating an exemplary manner in which thetest results can be post processed.

FIG. 32 is a block diagram illustrating an exemplary graphicalrepresentation computation computation.

FIG. 33 is a block diagram showing four examples in which the predictedfaulty behaviors and the observed behavior have different relations.

FIG. 34 is a block diagram illustrating an actual-failing-bitspositioning caused by two defects.

FIG. 35 is a block diagram illustrating the observed failing patternscaused by two defects.

FIG. 36 is a graph showing the distribution of the distance betweenneighboring signals lines relative to a minimum distance d₁ for anexemplary integrated circuit.

FIG. 37 is the graph of FIG. 36 overlaid with predicted defect data anda predicted yield sensitivity curve for the exemplary integratedcircuit.

FIG. 38 is the graph of FIG. 36 overlaid with actual defect data and anactual yield sensitivity curve for the exemplary integrated circuit.

FIG. 39 is the graph of FIG. 37 overlaid with the graph of FIG. 38 andshowing a comparison between the predicted and actual results.

FIG. 40 is a block diagram showing two exemplary features that couldpotentially have a corner-to-corner bridging defect or a side-to-sidebridging defect.

FIG. 41 is a block diagram showing a buffer haying two equivalent fault

FIG. 42 is a block diagram of a net having faults that can be observedin two groups of scan cells, the groups being determined, for example,by an embodiment of a pareto chart computation procedure.

FIG. 43 is a block diagram illustrating the possibility of dies on awafer failing due to systematic mechanisms.

FIG. 44 is a block diagram illustrating an exemplary wafer defect map.

FIG. 45 is a block diagram illustrating the exemplary wafer defect mapof FIG. 44 after so-called “hot nets” are identified.

FIG. 46 is a block diagram illustrating an exemplary fanout-free regionwherein a stem signal line is located.

FIG. 47 is a block diagram schematically a yield analysis methodaccording to one exemplary embodiment of the disclosed technology.

FIG. 48 is a block diagram showing an exemplary computer network as canbe used to perform any of the disclosed methods.

FIG. 49 is a block diagram showing an exemplary distributed computingenvironment as can be used to perform any of the disclosed methods.

FIG. 50 is a flowchart for performing an exemplary component of thedisclosed technology (test pattern generation) utilizing the network ofFIG. 48 or the computing environment of FIG. 49.

DETAILED DESCRIPTION General Considerations

Disclosed below are representative embodiments of methods, apparatus,and systems having particular applicability to testing, analyzing, andimproving the yield and quality of integrated circuits that should notbe construed as limiting in any way. Instead, the present disclosure isdirected toward all novel and nonobvious features and aspects of thevarious disclosed methods, apparatus, and systems, and theirequivalents, alone and in various combinations and subcombinations withone another. The disclosed technology is not limited to any specificaspect or feature, or combination thereof nor do the disclosed methods,apparatus, and systems require that any one or more specific advantagesbe present or problems be solved.

Moreover, any of the methods, apparatus, and systems described hereincan be used in conjunction with the manufacture and testing of a widevariety of integrated circuits (e.g., application specific integratedcircuits (ASICs), programmable logic devices (PLDs) such as afield-programmable gate arrays (FPGAs), or systems-on-a-chip (SoCs)),which utilize a wide variety of components (e.g., digital, analog, ormixed-signal components).

Although the operations of some of the disclosed methods are describedin a particular, sequential order for convenient presentation, it shouldbe understood that this manner of description encompasses rearrangement,unless a particular ordering is required by specific language set forthbelow. For example, operations described sequentially can be rearrangedor performed concurrently. Moreover, for the sake of simplicity, theattached figures may not show the various ways in which the disclosedmethods, apparatus, and systems can be used in conjunction with othermethods, apparatus, and systems. Additionally, the description sometimesuses terms like “determine” and “identify” to describe the disclosedtechnology. These terms are high-level abstractions of the actualoperations that are performed. The actual operations that correspond tothese terms will vary depending on the particular implementation and arereadily discernible by one of ordinary skill in the art.

The disclosed embodiments can be implemented in a wide variety ofenvironments. For example, any of the disclosed techniques can beimplemented in whole or in part in software comprisingcomputer-executable instructions stored on tangible computer-readablemedia (e.g., tangible computer-readable media, such as one or more CDs,volatile memory components (such as DRAM or SRAM, or nonvolatile memorycomponents (such as hard drives)). Such software can comprise, forexample, electronic design automation (EDA) software tools (e.g., anautomatic test pattern generation (ATPG) tool). The particular softwaretools described should not be construed as limiting in any way, however,as the principles disclosed herein are generally applicable to othersoftware tools. Circuit designs that result in defects that are detectedusing the disclosed techniques can in some circumstances be repaired.

Such software can be executed on a single computer or on a networkedcomputer (e.g., via the Internet, a wide-area network, a local-areanetwork, a client-server network, or other such network). For clarity,only certain selected aspects of the software-based implementations aredescribed. Other details that are well known in the art are omitted. Forexample, it should be understood that the disclosed technology is notlimited to any specific computer language, program, or computer. For thesame reason, computer hardware is not described in further detail. Anyof the disclosed methods can alternatively be implemented (partially orcompletely) in hardware (e.g., an ASIC, PLD, or SoC).

Further, data produced from any of the disclosed methods can be created,updated, or stored on tangible computer-readable media (e.g., tangiblecomputer-readable media, such as one or more CDs, volatile memorycomponents (such as DRAM or SRAM), or nonvolatile memory components(such as hard drives)) using a variety of different data structures orformats. Such data can be created or updated at a local computer or overa network (e.g., by a server computer).

Overview of an Exemplary Yield Analysis Method

Exemplary desirable embodiments of the disclosed technology relate tothe Design-for-Manufacturability (DFM) of integrated circuits. DFM rules(sometimes referred to herein as “design manufacturing rules”) can beused to determine potential production aberrations, referred to hereinas “defects”. Other techniques, such as simulation of layoutprintability across the process window, can also be used to identifydefects. According to certain embodiments of the disclosed technology,the actual distribution of classes of defects and of individual defectsdesirably can be determined using integrated circuits actually beingproduced for shipment by integrated circuit foundries (for example,integrated circuit designed for functional use in an electronic device).In other words, features present in an integrated circuit design inproduction can be analyzed instead of test structures on a speciallydesigned test chips. Consequently, the need or use of specially designedtest chips can be eliminated or significantly reduced. Further, byanalyzing these distributions, the DFM rules can be modified to increasethe yield in the production of the integrated circuit and of otherintegrated circuits that use the same set of DFM rules.

FIG. 47 is a block diagram schematically illustrating a yield analysismethod (4700) according to one exemplary embodiment of the disclosedtechnology. In the illustrated embodiment, yield improvement is achievedby performing a test-based analysis of the underlying DFM rules or of anextracted or modified set of DFM rules derived at least in part from aninitial set of DFM rules. Based upon these DFM rules, the defects thatare most likely to appear can be extracted from the layout of theintegrated circuit, and high-quality test pattern sets can be generatedto target the detection of these defects. For example, and withreference to FIG. 47, a fault/defect extraction component (4710) (forinstance, a physical verification tool or other appropriate EDA softwaretool) can receive a set of defect rules (4702) (for example, DFM rulesprovided by a foundry or a rules set created by an earlier iteration ofthe method (4700)) and a design of an integrated circuit (4704) (forinstance, a layout description of the geometry of the integrated circuitdesign, such as a GDSII or Oasis file).

The fault/defect extraction component (4710) can operate to extractpotential defects from the integrated circuit design, wherein theextraction is based at least in part on one or more of the defect rules(4702). For instance, one or more defect extraction rules can bedetermined from the defect rules and applied to the circuit design.Exemplary techniques, for performing defect extraction rule creation andextraction are discussed in greater detail below. In some embodiments,the defects can be categorized into several classes and subclasses,which are parameterized by specific features of the class. A faultsimulation/test pattern generating component (4712) (such as anautomatic test pattern generation (ATPG) tool) can receive the extracteddefects and operate to create one or more test patterns targeting theextracted defects. To generate the test patterns, the test patterngenerating component (4712) can use a different representation of theintegrated circuit, such as a netlist (4713). In addition, the faultsimulation/test pattern generating component (4712) can receive existingtest patterns (4711) and simulate or otherwise characterize them for theextracted defects. Furthermore the fault simulation/test patterngenerating component (4712) can generate incremental test patterns.Exemplary techniques for performing test pattern generation for theextracted defects are discussed in greater detail below. The faultsimulation/test pattern generating component (4712) can also produce adefect data base (4720) (sometimes referred to as a fault dictionary,fault thesaurus, or defect dictionary).

The integrated circuit design is manufactured (4705) and tested (4714)(for example, using a tester or ATE). During testing (4714), failinformation for one or more integrated circuits can be recorded. Thetesting can be performed, for example, using the generated test patternstargeting the extracted defects. In certain embodiments, the integratedcircuits tested are production circuits, not specialized test chips. Atest analysis component (4716) can receive and evaluate the failinformation during production. In certain situations, and according tosome embodiments of the disclosed technology, incremental simulation anddiagnosis procedures can be used in order to increase the defect classresolution. Based at least in part on the test-result analysis,information concerning failing design properties can be collected andstored, for example, as diagnostic results (4722). A diagnostic resultsanalysis component (4718) can be used to analyze the results using oneor more statistical methods (described in greater detail below) and todisplay the results as one or more graphical representations (4719). Forexample, according to one exemplary embodiment, the results can bedisplayed in a pareto chart (for example, a graphical representationfocusing, for instance, on potential design defects in design featuresand classes or subclasses of such defects). The diagnostic results(4722) can be used in multiple ways, such as to compute the yield forthe integrated circuit production or to estimate the defects-per-million(DPM) (sometimes referred to as the “escape rate”). In someimplementations, the presumed yield data is continuously updated inorder to improve the accuracy of the predictions. Further, the outcomeof the analysis of the diagnosis results can be used to analyze the DFMrules and defect-extraction rules. From this analysis, DFM rules anddefect-extraction rules (whether derived from DFM rules orindependently) can be related to the cause of the failing devices.Improvements of the DFM rule set and defect-extraction rule sets canthen be generated (for example, in some embodiments, the improved rulesare automatically generated). The new rule sets, when implemented, canbe used to increase the quality or yield of the production of theintegrated circuit and can also improve the initial yield of theproduction of other integrated circuits. The improvements to the rulesets can include, for example, additions, deletions, and modificationsof existing rules, but can also involve the creation of new defectclasses or the refinement of classes, which can form at least part of anew set of defect rules (4702). Thus, the yield analysis procedureillustrated in the block diagram (4700) can be repeated for a set ofrules with one or more rules that have been revised or modified by aprevious application of one or more of the components of the illustratedyield analysis process. In addition, analysis with fail data setsgathered over time can be compared to each other in order to identifytrends in the occurrence of defects. These decisions are generallyperformed at yield enhancement decision stage (4724) and are typicallymade manually. Through the use of such a method, the necessity ofso-called test chips can be greatly reduced or eliminated entirely.

Among other possible advantages, embodiments of the disclosed technologycan be used to improve the yield and quality of the production of anintegrated circuit and of future integrated circuits by improving theDFM rules, the defect-extraction rules, and/or the defect ranking. Asexplained in more detail below, embodiments of the disclosed technologycan comprise one, some, or all of the following method acts:

-   -   Deriving defect-extraction rules from defect rules such as DFM        rules;    -   Extracting defects from a description of the integrated circuit        using the derived defect-extraction rules and additional        defect-extraction rules;    -   Assigning a ranking to each extracted defect based on the        description of the integrated circuit. (In some implementations,        the ranking is continuously updated (e.g., using data collected        from testing devices testing the described integrated circuit or        other integrated circuits));    -   Filtering the extracted defects based at least in part on, for        example, a ranking or location of the defect in the layout of        the integrated circuit;    -   Predicting the yield and quality of the integrated circuit;    -   Mapping the extracted defects into fault models;    -   Generating, qualifying, and/or ordering input stimuli (for        example, test patterns) based at least in part on the extracted        defects and their ranking;    -   Generating a dictionary with respect to the generated input        stimuli;    -   Applying test stimuli to manufactured chips and collecting        test-result data;    -   Processing test-result data. (for example, diagnosing the test        results) using the dictionary;    -   Analyzing the results of diagnosis for the purpose of providing        data that can be used in the following method acts:        -   Modifying, adding, and/or deleting DFM rules based at least            in part on the analysis of the diagnosis results;        -   Modifying, adding, and/or deleting defect-extraction rules            based at least in part on the analysis of the diagnosis            results;        -   Modifying the defect ranking based at least in part on the            analysis of the diagnosis results;        -   Diagnosing defects not originally included in the            dictionary. This diagnosis can lead to the modification of            the dictionary and/or addition of new or the modification of            old DFM rules or defect-extraction rules, or both kind of            rules; and    -   Comparing a number of analysis result sets in order to compute        and display trends with respect to the distribution of defects        and defect classes.

In some implementations of the general method, such as the generalmethod shown in FIG. 47, the method is applied to an integrated circuithaving a scan-chain-based design, which can further include on-chipcompression logic. Further, the general method is applicable inenvironments where the exchange of information is restricted.

As noted, certain embodiments of the exemplary general method involvethe extraction of defects based on DFM Rules (for example, using defectextraction component (4710)). In some implementations, for example, oneor more defect-extraction rules can be derived from one or more DFMrules. Further, the derived defect-extraction rules can comprise rulesthat are “tightened” and “loosened” in multiple ways with respect to therespective underlying DFM rules, with respect to the description of theintegrated circuit, and/or with respect to external stimuli. Thesevariations of the defect-extraction rules can help increase theresolution in determining and analyzing the failing of the respectiveunderlying DFM rule. One or more defect candidates can be extracted froma description of the integrated circuit using the tightened and looseneddefect-extraction rules. Further, one or more defect candidates can beextracted out of a description of the integrated circuit using anadditional set of defect-extraction rules not present or implied by theoriginal defect rules. According to one implementation, for instance,the defect-extraction procedure adds at least a nominal set of defectsrepresenting the worst case scenarios of each defect class to the set ofextracted defect candidates. The extraction method can mark thesedefects as special worst-case defects. In some implementations, one ormore parts of the integrated circuit description can be designated suchthat no defects are extracted therefrom when using the above-mentionedsets of defect-extraction rules.

The occurrence of a defect within each comparable class of defects canbe ranked using the description of the integrated circuit, the tightenedand loosened defect-extraction rules, and/or the respective underlyingDFM rules. The occurrence of a class of defects can also oralternatively be ranked using the description of the integrated circuit,the tightened and loosened defect-extraction rules, and/or therespective underlying DFM rules. In certain implementations, historicaldata can be taken into account when computing either or both of theserankings. The defects can further be ranked by overlaying the ranking ofthe individual defect within each class of defects with the ranking ofthe respective class. Further, the achievable yield can be predictedbased on the description of the integrated circuit, the tightened andloosened defect-extraction rules, the respective underlying DFM rules,and/or the ranking of the defects and classes of defects. Also, rankingwithin and across classes can be accomplished by re-ranking based onresults of the diagnostic result analysis (4718) of either the currentdesign or of results achieved from a comparable earlier design. Filterscan also be applied to select the extracted defects based on suchparameters as the ranking of the defects or certain property of thedefects, such as location within the layout of the integrated circuits.

Some embodiments of the exemplary general method involve a processtermed generally “DFM rule learning,” which involves improving one ormore DFM rules. For example, in some implementations, the DFM rules areimproved based on the outcome of the testing of one or more integratedcircuits. This improvement can comprise the modification of DFM rules,the addition of DFM rules, and/or the dropping of DFM rules. One or moreof the tightened and loosened defect-extraction rules can also oralternatively be improved. This improvement can likewise comprise themodification, of defect-extraction rules, the addition ofdefect-extraction rules, and/or the dropping of defect-extraction rules.The assumed ranking of the defect classes and/or the individual defectscan also be improved based on the outcome of the testing of one or moreintegrated circuits.

Embodiments of the exemplary general method also involve the generationof test patterns targeting one or more of the extracted defects (forexample, by test pattern generation component (4712)). For example, oneor more defects from one or more classes of defects can be mapped to oneor more corresponding faults associated with one or more fault models.Since multiple mappings are possible for some defects, thedefect-to-fault mapping can be directed (e.g., via external stimuli). Anetlist description (for example, netlist (4713)) of a design can bemodified to enable design-for-test procedures like test patterngeneration, simulation, and fault simulation to support defect-basedtesting by adding or deleting gates, or by adding or deleting signallines, or both. In some implementations, the patterns can be reorderedin order to enhance the defect resolution and/or the defect coverage.The pattern reordering can be performed while considering other, storedinformation. In certain implementations, a set of target defects, aswell as the tasks defining what to do with the defects in the set, canbe selected (e.g., manually or automatically). The set can contain oneor more defect and have one or more tasks selected for it. Using thisset of defects and tasks, test pattern generation can be performed. Forexample, test pattern generation can be performed to generate one ormore tests for one or more of the named defects in the set of targetdefects, or to generate one or more tests that distinguish betweensubsets of the target defects in the set. Each of these subsets cancontain one or more defects. The faults related to a set of targetdefects and tasks can be selected so as to increase the chance ofsuccessful test pattern generation (e.g., by analyzing the interactionof the faults and potentials to fulfill the tasks on the faults).Further, in certain implementations, the addition of a candidate testpattern for the set of target defects and tasks can be delayed accordingto an analysis of the effects this candidate test pattern will have onthe overall quality of the test pattern set and defect set (especiallywith respect to defect resolution). This analysis, for example, candetermine that the candidate test pattern for the set of target faultsand tasks should not be use. The analysis can determine that the testpattern generation for the set of target faults and tasks should beabandoned, or that the generation of a different candidate test patternfor the same or a modified set of target defects and tasks should beperformed. In some implementations, the fault simulation and/or testpattern generation that is performed supports multiple fault modelssimultaneously. In some implementations, faults mapped from one or moresets of defects and test patterns detecting these faults can beidentified so that the defects, faults, and test patterns can be removedfrom further consideration without having to simulate the entire testpattern set. Certain implementations are further configured to modifyintegrated output response compaction schemes in order to increase thedefect resolution and/or to increase the defect resolution by adding aselector stage to the mentioned output response compactor.

Embodiments of the general method can also involve a process known as“yield loss mechanism learning.” For example, in certainimplementations, the pareto chart of yield loss mechanism's is computed(for example, by test analysis component (4716) and/or diagnosticresults analysis component (4718)) by analyzing fail data of productionintegrated circuits and using precomputed information stored, forexample, in a defect dictionary (it should be noted that the term“dictionary” and “thesaurus” are used interchangeably in thisdisclosure). Miscellaneous defects that cannot otherwise be identifiedas belonging to any classes can be analyzed (for example, by advanceddiagnosis component (4726)) so that new information can be learned andincorporated into the defect rule set, the defect extraction rule set,and defect dictionary. The defect dictionary can also be updated basedon the new defect-extraction-rule set. The production testing fail dataassociated with each defective integrated circuit can be analyzed, andthe class of the defects that caused the failure identified. Thestatistical data can be analyzed and calibrated to minimize the averageprediction error due to the equivalent defects that cannot bedistinguished, so that the computed pareto chart for example of yieldloss mechanisms can achieve higher precision.

FIG. 1 is a block diagram illustrating more particularly the exemplarymethod for performing yield analysis illustrated in FIG. 47. Theexemplary method shown in FIG. 1 is subdivided into four sections,identified as Section I, II, III, and IV in FIG. 1. For ease ofpresentation, the various sections and procedures therein are sometimesreferred to as being actors of certain actions, though it should beunderstood that the procedures described are typically implemented ascomputer-implemented methods. Section I concerns the generation ofdefect-extraction rules (3), a list of defects (9), and a ranking (6)(for example, by fault-defect extraction component 4710). The defects(9) are extracted from the layout description (5) of the integratedcircuit (for example, a GDSII file). In certain embodiments, this listof defects (9) is not explicitly represented and communicated betweenSection I and Section II, but is instead represented implicitly. Some ofthe defect-extraction rules (3) can be automatically derived (2) from agiven set of DFM rules (1), according to which the integrated circuitwas designed, as shown in Subsection IA. Section II concernsdefect-based test pattern generation, simulation, and patternoptimization (13) (for example, by test pattern generation component4712). This section can produce a high-quality test pattern set (17)with respect to defect coverage and especially to defect resolution ofclasses and subclasses of defects. A class can be defined by non-deriveddefect-extraction rules (4) and by DFM rules (1), and subclasses cancomprise the derived respective defect-extraction rules (3). Section IIconcerns the application (19) of the test pattern set (17) to devices(18) in an ATE. Section IV concerns the processing (21) of test-resultdata (20) from the devices tested in Section III (for example, by testanalysis component 4716 and/or diagnostic results analysis component4718). The test-result data is evaluated, for example, with a dictionary(16), generated by Section II. A number of analyses can be performed onthe data. One type of analysis leads to the display of the results ofthe tested devices using so-called “pareto charts” (22). Another type ofanalysis (23) provides data that can be used to update the ranking ofthe defects and defect classes (24). This information is fed back intoSection I for an improved defect ranking and yield prediction. Yetanother type of analysis (25) focuses on the set of currentdefect-extraction rules. This analysis investigates if some of the DFMrules (1) from which the defect-extraction rules (3) were derived shouldbe modified. This information can be used to improve the DFM rules, andthus the yield, for the current integrated circuit (e.g. by means of aredesign or a mask modification (27)). In addition, the improved DFMrules can lead to higher initial yield of the next design, which isbased on the now-improved DFM rules. A further aspect of this analysisis to feedback the modified (26) defect-extraction rules (3) (4), forexample, to increase the defect resolution or to include defects thatwere not considered before.

In the following sections, the various procedures performed in thegeneral method shown in FIG. 1 are described in greater detail. Theparticular procedures described should not be construed as limiting inany way, however, as they describe particular representativeimplementations of the procedures shown in FIG. 1. Any of the describedprocedures can be used separately or independently as part of othersystems.

The discussion of the exemplary procedures assumes the production of anintegrated circuit using DFM rules for which there is not yet muchexperience and knowledge. Traditionally, large quantities of test chipswould have been produced to learn more about the DFM rules and theproduction challenges. Here, it is shown how embodiments of thedisclosed method can help to reduce the requirements for test chips and,at the same time, increase the quality of knowledge gained.

Throughout the discussion, two DFM rules are considered by way ofexample. It should be understood, however, that the described rules arefor illustrative purposes only and that the embodiments described arenormally applied to a much larger number set of DFM rules. The firstexample rule concerns the minimum distance between two signal lines. Thesecond example rule concerns the layout geometry of the ends of signallines if there is a via connection. The discussion below focuses atfirst on the method as shown in FIG. 1 and explains howdefect-extraction rules are derived from DFM rules and how defects areextracted and ranked. Initially, the example skips details about theactual test pattern generation and test-result-data evaluation forpurposes of readability. The example continues with the analysis offailing defect-extraction rules and relates this information back to theunderlying DFM rules. Finally, details about exemplary methods of testpattern generation are described, followed by details of exemplarymethods for evaluating the test-result data. The last section describesthe application of the general method to circuit designs having outputresponse compactors.

DFM Rule Based Defect-Extraction-Rule Derivation

Referring to subsection Ia of FIG. 1, the exemplary flow starts with aset of DFM rules (1) and the layout data of an integrated circuit (5).From these DFM rules, defect-extraction rules (3) are to be derived (2).As noted above, DFM rules typically comprise recommendations orsuggestions that reflect different levels of emphasis of the rules inthe DFM set, and different requirements to follow them more or lessstrictly. However, for illustrative purposes only, the various types ofrules are not distinguished in the discussion below. In implementationsof the described methods, however, the differences among the rules areaccounted for.

FIGS. 2 and 3 show examples of DFM rules. FIG. 2 depicts a rule thatsuggests that two parallel signal lines (for example, lines (201),(202)) should be separated from each other by a distance of d₁. FIG. 3shows a similar rule that suggests that signal lines (for example, line(301)) should be separated by a distance of d₂ from any other layoutfeature (for example, feature (302)). Other DFM rules can describe, forexample, how two signal lines in different layers are to be connectedusing a via FIGS. 4, 7, and 8 show examples of such rules.

In general, DFM rules are used to ensure that the integrated circuit isactually manufacturable using the process and technology that is impliedby the DFM rules. With reference to FIG. 1, the set of DFM rules (1) istranslated (2) into a set of defect-extraction rules (3). As an example,refer again to FIG. 2. Let the DFM rule read as follows: M1: For allparallel signal lines in the same layer, the minimum distance is d₁.

According to one exemplary embodiment, the rule derivation procedure (2)transforms M1 into a set of defect-extraction rules (3) as follows. Thelayout (5) of the integrated circuit is analyzed. This analysisidentifies possible defect candidates and their respective propertiesand distribution. It also takes external stimuli into account. For thesake of this example, assume that the user specified that there arecurrently production problems with the device that result in anincreased likelihood of certain kind of defects (e.g., bridgingdefects). The analysis within the rule derivation method can addressthis problem. For the case where bridging defects are specified, forexample, the analysis can define more bridge-defect-extraction rulesthan it would normally do. The resolution on the defect classes can beaccordingly increased, thereby providing valuable information to theproduction engineer.

In addition, the analysis could determine that design rule M1 has beenviolated in the layout (5). Thus, appropriate defect-extraction rulescan be added to the set. For example, the distribution of the minimumdistance between pairs of neighboring signal lines (limited by an upperfactor of here d₁+35%*d₁) could be as shown in the graph of FIG. 36.Note that y-axis is omitted from FIG. 36, as it used to schematicallyrepresent different parameters throughout the graphs shown in FIGS.36-39. With respect to the distribution curve shown in FIG. 36, forinstance, the y-axis schematically represents the number of neighboringsignal lines having the corresponding distance shown on the x-axis.

Based on this distribution of candidates, the rule derivation procedure(2) distributes the defect candidates into classes with similar minimumdistance. This classification can help increase the resolution ofproduction faults with respect to design rule M1. This analysis can alsobe used to estimate the number of defect candidates before actuallyextracting them. The user can influence the defect extraction method atthis point, if, for example, the number of potential defect candidatesbecomes too large. For the above distribution, the following exemplarydefect-extraction rules (3) can be generated for the DFM rule M1 by therule derivation procedure (2):

-   -   E1(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E1) is defined by: d₁−3%*d₁≦d_(E1)<d₁    -   E2(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E2) is defined by:        d₁−8%*d₁≦d_(E2)<d₁−3%*d₁    -   E3(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E3) is defined by: d_(E3)<d₁−8%*d₁    -   E4(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E4) is defined by: d_(E4)=d₁    -   E5(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E5) is defined by: d₁<d_(E5)≦d₁+4%*d₁    -   E6(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E6) is defined by:        d₁+4%*d₁<d_(E6)≦d₁+8%*d_(i)    -   E7(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E7) is defined by:        d₁+8%*d₁<d_(E7)≦d₁+13%*d₁    -   E8(M1): Extract all pairs of signal lines in the same layer        whose minimum distance d_(E8) is defined by:        d₁+13%*d₁≦d_(E8)≦d₁+20%*d₁

It is possible that a pair of signal lines runs parallel to each otherat different distances for different sections of the signal lines,causing that pair to be selected by multiple extraction rules. Thedefect probability computation later in the flow should desirably takethis into account.

A second exemplary DFM rule M2 to consider is a geometric one.Specifically, M2 defines the geometry at the end of signal lines in thecase when there is a via connecting the signal line to another in anadjacent layer. FIGS. 4, 7 and 8 show different possibilities of thegeometry at the end of the signal lines. All of the geometries connectsignal (401) to signal (402) through via (403) but they differ in theirreliability. FIG. 5 illustrates the problem. The ends of signal line(501) are not actual squares, but assume a round shape due to a numberof production issues. This can cause via (502) to be partially off thesignal contact, which in turn limits its capability of establishing acorrect connection between the connected signals. FIG. 6 shows onepossible solution to the problem: The via (502) is relocated a bit awayfrom the signal end. FIGS. 7 and 8 show other such examples. Therealizations shown in the FIGS. 4, 7, and 8 fail with a differentprobability (i.e. they have a different impact on the yield), with FIG.8 showing the most reliable connection geometry of the group. Therefore,the DFM rule M2 can read as follows:

-   -   M2: If a signal line is connected to another signal line with a        via at the end of the signal line, the geometry should be        analogous to FIG. 8.        It can be extremely difficult or impossible to extract all        signal lines which have vias at their end. The defect-extraction        rules should therefore select the defect candidates carefully.        For example:    -   E1(M2): Extract n₁ signal lines, for which all respective        connections follow FIG. 4.    -   E2(M2): Extract n₂ signal lines, for which all respective        connections follow FIG. 7.    -   E3(M2): Extract n₃ signal lines, for which all respective        connections follow FIG. 8    -   E4(M2): Extract n₄ signal lines, which were not selected by        E1(M2) through E3(M2).

Rules E1(M2) through E3(M2) are desirable for a good defect resolutionBut the respective sets of extracted defects could be empty. Rule E4(M2)adds a reliability test to the test pattern sets. Because one cannottarget all problematic vias, only the most likely signal lines to failare selected as targets. If there is a general problem with the vias,many tests will fail, not only the ones for the DFM rule M2. But theseextraction rules add a certain resolution capability to the test patternset.

Similar defect-extraction-rule derivations can be computed for other DFMrules (1). The defect-extraction rules derived collectively form the setdenoted by (3) in FIG. 1. The derivation process (2) should ensure thatfor each defect-extraction rule, it remains possible to determine fromwhich DFM rule it was generated. For example, there can be a unique IDassigned to each DFM rule. Each defect-extraction rule translated fromthe same DFM rule can share this ID as part of its data structure.

Besides the DFM-based defect-extraction rules (3), there is another setof defect-extraction rules (4) that can be created and used. This setfocuses on traditional defect-limited yield loss aspects, which are notcovered by the DFM-based defect-extraction rules. One example of thiskind of rule targets inline resistance of signal lines, which in turnalters the speed with which a transition of voltage levels travelsthrough the signal line. An additional subset of rules in set (4)defines areas for which no defect shall be extracted. Such areas are,for example, memories, which have their own self-test.

Defect Extraction

Based on the defect-extraction rules (3) (4), the actual defectcandidates are extracted using the layout description (5) of theintegrated circuit. Once the extraction rules are in place, theextraction itself (7) is well understood, and can be achieved using oneof many available tools (e.g., Calibre® from Mentor GraphicsCorporation). Extraction (7) generates a list of potential defects (9).

An extracted defect can be defined by the data describing the actualdefect, like location and physical properties. Additional data can beassociated with each defect. For example, in one exemplaryimplementation, the defects in the list (9) have one, some, or all ofthe following additional properties:

-   -   1. A unique identifier,    -   2. An identifier disclosing the rule from DFM-effect extraction        rules (3) and/or test-defect extraction rules (4) corresponding        to the defect extraction rule that caused the inclusion of the        respective defect in the list of defects;    -   3. An identifier disclosing the defect extraction rule that        caused the inclusion of the respective defect in the list of        defects;    -   4. The location of the defect in the layout of the integrated        circuit;    -   5. One or more physical parameters of the defect, such as        length, width, resistance, and/or capacitance;    -   6. An indicator of whether the defect belongs to a special class        of defects (for example, a worst-case defect of each class of        defects); and    -   7. A ranking. According to one implementation, the ranking        corresponds to the defects probability;

Item 1 is typically used to relate faults (which will be derived fromdefects using the methods of ATPG, fault simulation, and patternoptimization) to the original defect. There could be more than one faultderived from a single defect

Items 2 and 3 are used, for example, in the analysis of theeffectiveness of the rules, which in turn feeds back to the addition,deletion, or modification of the defect-extraction rules and/or thedesign manufacturing rules.

Item 4 can be used for identifying frequently failing locations and forguiding physical failure analysis.

Item 5 can be used for estimating the sensitivity of the defects tovariation in physical parameters.

Item 6 is used to flag the occurrence of defects that were notnecessarily the target of the normal defect-extraction rules. With thehelp of these specially marked defects, it is possible to cover all ornearly all of the possible defect classes. These specially markeddefects can be used to give the user an early warning of, for example,drifting production parameters, before they become statisticallysignificant. For example, one set of inline resistive defects cancontain the five longest signal lines in a specific metal layer.Initially, the test patterns that would detect these defects fail veryrarely; however a few weeks later, these test patterns fail more often.Although the total number of fails may be statistically insignificantwith respect to the overall test result of the device, a statisticallysignificant increased failing rate with respect to these special defectscan give the production engineer an early warning of a problem buildingup before it actually impacts the yield.

Item 7 helps the described method to correctly rank the defects of alldifferent kinds.

Ranking

There are at least two ranking schemes that can be used alone ortogether to rank the extracted defects. A first exemplary rankinginvolves ranking the defects within each class. This means that theranking does not represent an absolute number among all possible defectcandidates, but rather is specific to a particular class. For example,the ranking for all bridge types of defects can be comparable, and theranking of all open or resistive vias can be comparable. This rankingcan be computed automatically. A second exemplary ranking is betweendefect classes and is typically not determined automatically withoutsome externally provided data. Information can be supplied, for example,that relates the classes of defects in a quantified manner.

A description is provided below of how historical data can be used topredict failing rates and to rank the defects. This historical data canbe gathered, for example, from earlier testing of the same integratedcircuit, or from testing of other integrated circuits that use the sameor similar DFM rules. A description is also provided of how defects ofthe same class can be ranked if no historical data is available. Anexemplary overall ranking procedure is also described.

FIG. 37 shows a graph of the distribution curve of FIG. 36 together witha dashed line showing the expected yield sensitivity curve. In thisexample, the yield sensitivity curve was derived from assumptions andexperience. With respect to the yield sensitivity curve, the y-axisschematically indicates the percentage of yield loss resulting fromsignal lines separated by the corresponding distances on the x-axis. Ingeneral, yield sensitivity indicates the expected yield loss for each ofthe subclasses (for example, the percentage of expected fails) and canbe used for ranking (for example, from highest yield sensitivity tolowest). Yield sensitivity data along with the actual number of defectcandidates in each subclass E1(M1) to E8(M1) can be used to compute theestimate of the number of expected fails due to the defects for eachextraction rule (shown as the step functions in FIG. 37). This data canalso be used to rank the defects (for example, from the highest numberof expected fails to the lowest). Remember that this example assumesthat there is not much knowledge about the DFM rules used and theproduction of devices using these rules. Therefore, the yieldsensitivity curve shown represents an educated first guess of theresponsible engineer. As explained in more detail below, the expectedyield loss can be compared to the actual test response data andconclusions drawn from the comparison.

An exemplary ranking of defects extracted with respect to DFM rule M2 ispresented in this paragraph. As discussed above, the probability offailing is different for the three possible geometries associated withrules E1(M2), E2(M2), and E3(M2). According to one exemplaryimplementation, the ranking of defects extracted due to rule E1(M2) ishigher than the defects extracted due to rule E2(M2), which is higherthan the defects extracted due to rule E3(M2). The ranking of defectsextracted due to rule E4(M2) depends on the actual number of occurrencesof the different geometries and will vary.

Note that it is not necessary that there exists a failing probabilityassigned to the defects to compute a ranking of defects within a class.However, if one wants to rank the classes of defects relative to oneanother, some additional data is typically used. In certainimplementations, default values are assumed, but actual data is usuallypreferred. Assume, for instance, that is known that the relationship offails between bridges and vias is 80:20. From this, a ranking betweenclasses can be computed in a straightforward fashion—specifically, in away that for every eight bridge defects selected according to their ownranking procedure, the next two highest ranking via defects areselected. Since actual defect data is assumed not to be available atthis point, this ranking comprises a first approximation. But since theflow does not typically require truncating the pattern set, coverage isusually not an issue. Potentially, a certain defect can be selectedsooner or later than it should have been selected. If the available dataallows it, the method (7) can give a yield estimate (8).

Test Pattern Generation and Production Testing.

After the list of defects (9) has been generated, the general methodshown in FIG. 1 enters Sections II and III: test pattern generation andoptimization, and test application. For purposes of maintaining theclarity of this description, the discussion of how the test patterns aregenerated is provided later. The following points concerning the testpatterns, however, should be kept in mind.

In certain embodiments of the disclosed technology, one or more of thetest patterns (17) can distinguish classes and, in certain embodiments,subclasses of defects. In addition, the test patterns can distinguishthe majority of defects, but only as a subordinated objective withrespect to the capability to distinguish classes and subclasses ofdefects. (In this discussion, it is assumed that each DFM rule defines aclass and each defect-extraction rule defines a corresponding subclass.)

For purposes of this discussion, to increase the defect coverage,N-detection patterns are assumed with a user-selectable N. That is, Ndifferent patterns are used to detect a given defect.

For purposes of this discussion, it is assumed that a fault dictionary(16) is generated together with the pattern set. The fault dictionarycan comprise, for: example, a table organized into rows, with each rowcontaining data for a test pattern. The rows, and therefore the testpatterns, can be in the same sequence the test patterns are listed inthe accompanying pattern set (17). A fault in the fault dictionary canbe described by carrying the ID of the defect it was derived from, afault type, the overall number of times the fault has been detected, andthe number of observation points the fault can be propagated to underthe current test pattern. Further, the fault dictionary can store only alimited amount of detection data. For example, for each fault, only thefirst k detecting test responses can be stored; and for any laterdetection, the test response is not stored but the detection stillcounted. For each test pattern, the observation points at which faultsdetectable by the test pattern can be observed in the netlistrepresentation of the integrated circuit can be listed in or discerniblefrom the fault dictionary. The detectable faults can be organized, forexample, as lists associated with each of the observation points listedfor the current pattern. Exemplary implementations of a fault dictionaryas can be used in connection with any of the described embodiments aredescribed, for example, in B. Chess and Tracy Larabee, “Creating SmallFault Dictionaries,” IEEE Transactions on Computer-Aided Design, Vol.18, no. 3, pp. 346-356 (March 1999), and V. Boppana, I. Hartanto, and W.K. Fuchs, “Full Fault Dictionary Storage Based on Labeled TreeEncoding,” in Proceedings of the VLSI Test Symposium, pp. 174-197(1996). Other exemplary methods for creating a fault dictionary as canbe used in any of the disclosed embodiments are also described below ina separate section.

It is assumed for purposes of this discussion that devices realizing theintegrated circuit (5) have been tested using the test pattern set (17)as illustrated in Section III of FIG. 1. Test result data (20) can beavailable either in real time (while production testing is still inprogress) or from a database storing earlier test results.

Test-Result Analysis

Section IV of FIG. 1 involves the processing and analysis of test-resultdata (21). A more detailed description of the analysis is provided in aseparate section below. In general, however, the test-result analysis isperformed to determine from the test result data (20) and the dictionary(16) which classes of defects have failed, and if possible, whichindividual defects. FIG. 31 is a block diagram showing an exemplarymanner in which the processing (21) can be performed. Process (21.1) isperformed to try to identify the defect, respectively the class orsubclass of the defect, which can beet explain the failing behavior ofthe integrated circuit. If necessary, incremental diagnosis (21.3) andincremental simulation (21.2) procedures are activated. For most failingtest patterns of the tested devices, the class or subclass of the defectmost likely responsible for the failing behavior can be determined andstored as diagnostic results (21.4). Unclassified failing devices caninclude among other possibilities, multiple defects, marginal failuressuch as noise related or signal integrity issues. The exemplary generalmethod of FIG. 1 continues with defect extraction rule analysis (25),wherein a data set containing the relation of the defect-extraction ruleto the number of identified defects for the rule can be produced. Foreach defect, the identifier of the extraction rule that was responsiblefor its inclusion in the list of target defects (9) is typicallyavailable. The graph of FIG. 38 displays this relation as a stepfunction for the example discussed above with respect to FIG. 36. Thatis, the step function shown in FIG. 38 schematically shows the number ofactual fails observed for each extraction rule. From the number ofactual fails for each of the extraction rules, and from the number ofcandidates covered by each rule, the actual yield loss per class ofdefect (yield sensitivity) is computed. The actual yield sensitivitycurve is displayed in FIG. 38 as a dotted line.

The graph of FIG. 39 compares the initial expected yield loss (dashedline) with the actual yield loss (dotted line) for the example discussedabove with respect to FIG. 36. FIG. 39 also shows a comparison of thetwo associated step functions indicating the number of expected andobserved defects, respectively, for each subclass of defect. As can beseen, the actual yield loss is much higher than the expected yield loss.More specifically, the following observations can be made: (1) the yieldloss is higher than expected for all subclasses; (2) the yield loss isabout two times higher for the defect-extraction rules E4(M1) to E7(M1);and (3) the yield loss for extraction rule E8(M1) is higher, but closeto the expected yield loss.

From the observations, the following two conclusions can be drawn: (1)DFM rule M1 is valid, but there is a problem in the production of theintegrated circuit; or (2) the production runs within optimalparameters, thus rule M1 should be modified. Further analysis can beperformed to help decide between conclusion 1 and 2, or a combinationthereof. For example, pareto charts (22) and other test result dataanalysis (21) can help an engineer find a conclusion.

The conclusions can lead, for example, to the following short term andlong term actions:

-   -   Short term: Refine the yield prediction and DPM estimate numbers        of parts shipped.    -   Long term: Determine if conclusion 1 or 2 holds by analyzing,        for example, other test result data and perform subsequent        failure analysis on selected devices.        The time difference between the actions mentioned above can be        significant. The turn-around time of the long-term action can        take many months. The required close analysis of failing devices        takes days or a few weeks. But the implementation of the        corrective action, let it be changes in the production line,        mask production, or redesign using a modified DFM rule M1, will        typically take a few months.

By contrast, the turn-around time of the short-term actions as outlinedin the following is only a matter of hours to a few days. Therefore; theshort-term actions can be important. In this example, one or more of thefollowing short-term actions can be initiated:

-   -   1. Modify the ranking of the defects to focus closer on defects        extracted from DFM rule M1;    -   2. Refine the extraction rules of the DFM rule M1, and reanalyze        present test result data;    -   3. Accordingly modify the defect-extraction rules to focus        closer on the problem;    -   4. Generate additional test patterns to better cover the        identified problem with higher resolution;    -   5. Generate additional test patterns to cover defects that may        not have been covered before;    -   6. Iterate 1. through 5. if necessary when additional test        result data is available; and    -   7. Conclude from 1. and 2. an improved DFM rule M1 for a        possible long-term solution.        Item 1 is relatively straightforward. The defect ranking can be        updated (24) using the corresponding actual defect occurrence        data (23) by replacing the expected yield loss data (shown in        the graph of FIG. 37) with the actual yield loss data (shown in        the graph of FIG. 38). In addition, the respective data in the        defect ranking description (24) used during defect extraction        (7) can be changed so that defect classes derived from DFM rule        M1 have a higher priority.

As explained in the following, items 2 through 5 can improve defectcoverage and increase the defect resolution for the test of the devicesrealizing the integrated circuit until the problem of low yield andquality is resolved. For example, the test and shipping of alreadyproduced devices of the integrated circuit can continue. However, due tothe increased likelihood of defects related to DFM rule M1, testing isdesirably improved to filter out more defects of this class in order toretain DPM requirements. Further, it is often desirable to generatesufficient high quality data to guide the automatic refinement of DFMrule M1, if this turns out to be necessary.

One possible method for increasing the resolution of the relevant defectextraction rules is to split the area covered by each defect-extractionrule E1(M1) through E8(M1) in half, thus doubling the number ofsubclasses. Another possible method, however, evaluates the defectextraction rule analysis data (25) to determine the number of candidatesin each new potential subclass, and can additionally account for theexpected and actual yield data. For example, because rules E4(M1)through E7(M1) showed substantially higher yield loss than the otherrules, they can be divided into two or more smaller subclasses. Theresolution requirements for the ATPG for the sections that were supposedto have higher yield than observed can thereby be increased.

In addition, for the case where M1 should be relaxed, what is now E7(M1)and E8(M1) can be located around the new minimum distance d_(1new). Tosupport the updated procedure (27) with high quality data, E7(M1) andE8(M1) can be divided into smaller subclasses as well too, and a newsubclass beyond E8(M1) can be generated.

Additionally, yield sensitivity predictions based on the test responsedata can be displayed for the new extraction rules similar to the graphof FIG. 38. Note that, in this case, some ambiguity is possible becausethe test pattern set (17) was not generated for distinguishing the newsubclasses. However, as mentioned above, the test pattern set generatedis likely to distinguish the subclasses sufficiently enough to give agood estimate. The new defect-extraction rules can comprise, forexample:

-   -   E1(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E1) is defined by: d₁−1%*d₁≦d_(E1)<d₁    -   E2(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E2) is defined by:        d₁−3%*d₁≦d_(E2)<d₁−1%*d₁    -   E3(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E3) is defined by:        d₁−8%*d₁≦d_(E3)<d₁−3%*d₁    -   E4(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E4) is defined by: d_(E4)<d₁−8%*d₁    -   E5(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E5) is defined by: d_(E5)=d₁    -   E6(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E6) is defined by: d₁<d_(E6)≦d₁+1%*d₁    -   E7(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E7) is defined by: d₁+1%        d₁<d_(E7)≦d₁+3%*d₁    -   E8(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E8) is defined by:        d₁+3%*d₁<d_(E8)≦d₁+6%*d₁    -   E9(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E9) is defined by:        d₁+6%*d₁<d_(E9)≦d₁+10%*d₁    -   E10(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E10) is defined by:        d₁+10%*d₁<d_(E10)≦d₁+13%*d₁    -   E11(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E11) is defined by:        d₁+13%*d₁<d_(E11)≦d₁+16%*d₁    -   E12(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E12) is defined by:        d₁+16%*d₁<d_(E12)≦d₁+20%*d₁    -   E13(M1): Extract all pairs of signal lines in the same layer,        which minimum distance d_(E13) is defined by:        d₁+20%*d₁<d_(E13)≦d₁+24%*d₁        These new defect-extraction rules for DFM rule M1 can be used to        replace the old defect-extraction rules for M1 in the set of        defect-extraction rules (3). In some embodiments of the        disclosed technology, the defect-extraction rule responsible for        extraction of a particular defect is known. Accordingly, for the        revised set of defect-extraction rules, the defect extraction        procedure (7) can update the respective extraction rule        identifications for the defects listed in the list of defects        (9) to account for the finer subclasses and extract defects for        the newly covered areas (for example, defined by E13(M11)).

For the revised rules, and according to one exemplary embodiment, theATPG procedure (13) does not change. More specifically, the ATPGprocedure still attempts to produce test patterns that distinguish theclasses of defects. It is likely, however, that the old test pattern set(17) already distinguishes many of the new classes, at least in part.Therefore, test pattern set (17) can be used as the original testpattern set (11), and ATPG can be performed with the new list ofdefects. For example, the original test pattern set (11) can besimulated in order to determine an initial classification of thedefects. ATPG can then compute top-up patterns and reorder the patternsas usual in order to distinguish the new subclasses as required.Overall, the additional effort spent in ATPG is considerably less thatgenerating a new test pattern set from scratch. The newly generated testpattern set can then be used to test more devices realizing theintegrated circuit, or, if requested, retest the previous devices.

For purposes of this discussion, assume that at some later time, thelong-term problem analysis concludes that there is nothing wrong withthe production line. Therefore, the decision has been made to modify DFMrule M1 and accordingly increase the required minimum distance d₁. TheDFM rules updating component (27) can determine a new minimum distanceout of the available data. In addition, the DFM rules updating component(24) can provide data used to produce an accurate yield prediction (8)based on actual test result data.

In the following section, a more detailed description of test-patterngeneration is provided.

Generation of DFM Test Patterns

Referring again to FIG. 1, in one exemplary implementation of thegeneral method, the ATPG component (13) computes a defect-based testpattern set (17), which can be applied to devices on an ATE. A faultdictionary (16) can also be generated, in which pattern and defectinformation is stored for easy retrieval and display. Various files (15)(e.g., lists of faults and defects) can also be stored.

The following section describes exemplary methods of defect-basedsimulation and test-pattern generation as can be used in embodiments ofthe disclosed technology. FIG. 9 is a block diagram showing oneexemplary method for performing the defect-based ATPG and patternoptimization (13) of FIG. 1. The defect-based ATPG and patternoptimization component (13) shown in FIG. 9 uses a netlist (12), whichis a different representation of the integrated circuit than describedby the layout (5), and a list of defects (9). A set of rules (10)defining the way these defects are going to be mapped into faults, andan optional set of patterns (11) are additional-inputs to thedefect-based. ATPG and pattern optimization component (13). Thedefect-based ATPG and pattern optimization procedure (13) can beconfigured to automatically substitute the fault mapping rules (10) withdefault rules in instances where the set is not defined. Thedefect-based ATPG and pattern optimization component (13) outputs adefect-based test pattern set (17) produced according to a desireddefect resolution and a corresponding dictionary (16). In addition,various files (15) and statistics (14) can be requested. Statistics caninclude metrics such as fault coverage, test coverage, defect coverage,and estimate of quality (DPM).

The optional pattern set (11) can be from any source. For example, thepattern set (11) can be a classical-fault-model-based test pattern set.Classical-fault-model-based means here that the patterns were generatedfor, for example, stuck-at faults, transition faults, path delay faultsand other such ‘classical’ fault models.

The defect-based ATPG and pattern optimization component (13) also usesa set of rules (10) describing the way the user wants the component tomap the extracted defects to faults. An example is bridging defects.There are multiple ways to define faults associated with a bridgedefect. Simple ones are wired-and or wired-or. Enhanced ones cancharacterize the bridge as a zero-resistance connection between the twonets, and the interpreted logic value of the voltage on the shortenednets can depend on the interpretation of the sink gates. However, theuser may want to define a bridge having a resistance of c Ohms per μm ofnet distance, and leave the actual computation to the tool. Thedefect-based ATPG and pattern optimization component (13) providesdefault rules.

Fault Mapping (13.1)

Referring now to FIG. 10, fault mapping (13.1) is a two-step processaccording to one exemplary embodiment. At first, the mapping methodevaluates the list of defects (9) and rules (10). In certainimplementations, the fault mapping procedure (13.1) can determinewhether the netlist (12) can support a proper defect to fault mapping.If the netlist (12) cannot, the netlist (12) can be modified in order toenable the fault-based ATPG and simulation to correctly compute andevaluate defect effects.

The fault mapping procedure (13.1) can map the defects into faults basedon, for example, user-selectable rules (10). As a result, adefect-enhanced fault list (A) can be generated. Note that, in someimplementations, there is only one fault list (A) used throughout thefault mapping procedure (13), and each step can alter data in the faultlist (A). For convenient presentation, different lists (A) will not bedistinguished in subsequent figures.

Note that the fault models used are typically more sophisticated thanthe traditional stuck-at or transition-fault models in order to modelthe behavior of the defect. Further, the mapping will sufficientlyabstract the defect in order to have a working fault model. In general,a wide variety of fault models can be used. In addition, faults ordifferent fault models are desirably supported in the ATPG and faultsimulation methods.

Defect Simulation and Pattern Optimization (13.2)

Referring now to FIG. 11, after the netlist has been modified in (13.1),and the defects mapped into faults, an optional defect simulationprocedure (13.2) can be performed if there is a pattern set (11)defined. This defect simulation procedure (13.2.1) determines which ofthe test patterns of the pattern set (11) (which can be generated usingtraditional fault models) are actually effective defect test patternsand which defects are detected by these test patterns. Optionally, theinitial defect-based test pattern set can be optimized with respect to adifferent goal the user wants to achieve (13.2.2). At (13.2.3), a firstdefect-based test pattern set is generated. Again, different files andstatistics can be requested (15), (14), and the initial pattern set(13.2.3) can be saved (17) together with the corresponding dictionary(16).

FIG. 12 is a block diagram showing in greater detail an embodiment ofthe defect simulation procedure ((13.2.1) of (13.2)). For the most part,(13.2.1) looks like a traditional fault simulation: the patterns in (11)are fault simulated using the faults in the defect-enhanced fault list(A). The defect simulation procedure can also add data into an internalversion (B) of the external fault dictionary. Similar to the defectenhanced fault list (A), there is usually just one copy of internaldictionary (13) used in the defect-based ATPG and pattern optimizationcomponent (13). In contrast to the enhanced fault list (A), whoseprimary purpose is to record the achievements of the test patterns sofar in the form of detected and undetected faults, internal dictionary(B) is mainly used to guide later optimization and pattern-generationprocedures to effectively achieve their respective goals. The internaldictionary (B) typically contains more information than is actuallystored in the fault dictionary (16) since the various optimization andtest-pattern generation procedures that can be applied usually requireincreased flexibility. For example, if the fault dictionary (16) is ak-detection dictionary (that is, detection information up to k times isrecorded for each fault) and the resulting data is stored in (16), theinternal dictionary (B) should at least also be a k-detectiondictionary. However, the quality of the final result can be increased ifinternal dictionary (B) is a k′-detection dictionary, with k′>>k, sinceoptimization methods, like the one explained below, then have moreoptions from which to choose a pattern. In addition, with the variationof k and k′, the memory demand of the defect-based ATPG and patternoptimization component (13) can be influenced significantly.

Among other acts, the defect simulation procedure (13.2.1) generates adefect-based test pattern set (13.2.1.3), which can be used in anoptional pattern optimization procedure (13.2.2). FIGS. 13-15 show ingreater detail three exemplary manners in which the pattern optimizationprocedure can be implemented (13.2.2.A, 13.2.2.B, and 13.2.2.C). Thethree procedures operate similarly, but their respective optimizationgoal is different. FIG. 13 (13.2.2.A) focuses on enhancing the defectresolution using resolution enhancement analysis (13.2.2.2). FIG. 14(13.2.2.B) tries to raise the defect coverage as fast as possible usingdefect coverage enhancement analysis (13.2.2.3). Finally, FIG. 15(13.2.2.C) is configured to find a compromise between defect resolutionand fast coverage increase. Note that in this exemplary embodiment, thepattern optimization procedure (13.2.2) is performed by employingpattern reordering. For example, the pattern reordering is performed inpart by pattern selection procedure (13.2.2.1), which interacts with theanalysis methods for either or both resolution and coverage enhancement,and with the defect-enhanced fault list (A) and the internal dictionary(B). With the help of the previously computed ranking, the patternselection procedure (13.2.2.1) can decide which pattern to select nextto achieve the different mentioned goals such as resolution enhancement,coverage enhancement, and the combination of these two, and subsequentlyupdate the defect-enhanced fault list (A) and the internal dictionary(B), and the resulting pattern set (13.2.2.4). An example ofgoal-directed pattern selection is given below.

In principle, the selection of the patterns can be considered a coverageproblem, with the additional property that the data of the unselectedpatterns can change after each selection because the selected patterncould represent the k-th detection for a defect d, and thus allsubsequent detections of d would not be stored in the dictionary.Therefore, finding an optimal solution is difficult or impossible forany, but the smallest integrated circuits. Usually, a so-called “greedy”approach produces acceptable results for such coverage problems.Therefore, one possible implementation of (13.2.2.1) is the greedyselection of a pattern, which splits the highest-ranking group ofundistinguished defect classes.

Consider the following example: for each test pattern p, and each defectd detected by p, a signature sig(p,d) is computed, with the property ofsig(p,d1)=sig(p,d2) if and only if the observation points for d1 arealso observation points for d2 and vice versa for test pattern p. Thismeans, if d1 and d2 have the same signature, they are notdistinguishable by p. Let sig(d) be a signature representing acombination of all sig(p,d) for all test patterns p up to this pointAgain, if sig(d1)=sig(d2), then the defects d1 and d2 are notdistinguishable, but this time by all test patterns so far. (Anexemplary implementation of this signature attached to each defect is alist of elements of the type (pattern number, list of observation pointnumbers). This implementation should not be construed as limiting,however, because it is mentioned here only to show that such a signatureexists.)

According to one exemplary implementation, the two highest-rankingclasses of defects C1 and C2 with respect to undetected defects in C1and C2 are found using the following:

$\begin{matrix}{{\max \left( {{\sum\limits_{p \in {C\; 1}}{{rank}(p)}} + {\sum\limits_{q \in {C\; 2}}{{rank}(q)}}} \right)},{p\mspace{14mu} {undetected}},{q\mspace{14mu} {undetected}}} & (1)\end{matrix}$

for all undetected defects p of C1 and q of C2. The highest rankingundetected defects d1 in C1 and d2 in C2 with sig(d1)=sig(d2) are thenfound. Note that a defect is called detected in a k-detection schemeonly if it has been detected k times or more. If coverage is not afactor in the optimization, the above-mentioned function rank(d) canreturn the ranking of the defect determined earlier. If coverage is tobe taken into account (for example, during test pattern optimizationprocedure (13.2.2.B) or (13.2.2.C)), then rank(d) can be a weighted sumof the ranking of the defect and expected coverage, (for example,measured in the size of the observation and controlling cones of thedefect).

It is also possible to take the current number of detections k′<k as adiminishing factor into account for the ranking of the defects. Forexample, the smaller k-k′ is, the larger the penalty, thereby allowinglower ranking defects that are not detected many times to be consideredearlier.

According to this exemplary implementation, the two defects d1 and d2represent the most profitable target. One can now find the nearest testpattern p in the old sequence of test patterns with sig(p,d1)≠sig(p,d2)and select it as the next test pattern for the reordered sequence oftest patterns. Note that for all patterns between the new and the oldposition of p, the combined signature sig(d) of the detected defects dcan change. However, this signature should be updated only for defectsthat are detected by p. Thus, if the next pattern reordering stepsconsider only defects that were not detected, by p for these patterns,recomputation of the respective signature is usually not necessary.Further, the signature typically does not need to be updated for allpatterns after the old position of p, though there can be at least oneissue. Namely, due to the limited number of detections k stored in theinternal dictionary (B), it is possible that the repositioned pattern pnow is the k-th detection, thereby invalidating the test patternproperty for d of a later pattern q. However, since it is known when adefect reaches the k-th detection, this special case can be easily takencare of. In general, the described pattern reordering procedure canproceed through the old sequence of patterns, and can resimulate andupdate the signatures after the end of the old sequence is reached. Thepattern selection procedure (13.2.2.1) can be iteratively repeated inorder to further improve the defect resolution. Although only twoclasses are distinguished in the above exemplary procedure, theprocedure can be modified to more generally apply to additional classes.

With reference to FIG. 16, the resulting pattern set (13.2.3) from thedefect simulation and pattern optimization procedure (13.2) is eitherthe defect-simulated (13.2.1.3) pattern set (11), which has no changedpattern order but no longer has; ineffective defect test patterns, orthe reordered version (13.2.2.4).

Defect ATPG and Pattern Optimization (13.3)

FIG. 17 is a block diagram showing an exemplary manner of performing thedefect-based test pattern generation and optimization procedure (13.3).Within FIG. 17 is the ATPG method (13.3.1), which generates (additional)defect-based test patterns. These patterns, together with the optionalpatterns of (13.2.3), are then optionally improved using an optimizationprocedure (13.3.2). The final defect-based test pattern set (13.3.3) canthen be computed and stored as the defect based test pattern set (17)together with its corresponding fault dictionary (16). Again, variousfiles (15) and statistics (14) can also be requested.

FIG. 18 is a block diagram showing an exemplary manner of performing thedefect ATPG (13.3.1) from FIG. 17. The defect selection procedure(13.3.1.1) selects one or more defects for ATPG (13.3.1.2). In addition,the defect selection procedure can select tasks that define for the ATPGwhat to do with the selected defects and their respective faults. Moredetail will be presented in the next paragraph, when the method ofdefect selection is explained. In case the ATPG (13.3.1.2) determinesfaults to be untestable, it can update the fault list (A) and thedictionary (B), using an updating procedure (13.3.1.5). Otherwise, theATPG (13.3.1.2) can make the generated test-pattern candidate availablefor defect simulation (13.3.1.3). The outcome of the simulation can thenbe analyzed at (13.3.1.4) and, if accepted, the candidate test patternwill be added to the defect-based test pattern set (13.3.1.6). In eithercase, both (A) and (B) are updated by an update procedure (13.3.1.5).

FIGS. 19 through 21 show three exemplary variations (13.3.1.1.A,13.3.3.1.B, and 13.3.1.1.C) of the defect selection procedure(13.3.1.1). The outline is similar to pattern optimization. For example,in the illustrated embodiments, a set of target defects (13.3.1.1.4) forthe ATPG, together with a specific task for the ATPG to accomplish onthis set of defects, is selected. This set can contain a set of defectsfor the ATPG to distinguish in order to enhance defect resolution (FIG.19, 13.3.1.1.A), to enhance coverage (FIG. 20, 13.3.1.1.B), or acombination thereof (FIG. 21, 13.3.1.1.C). By means of this targetdefect set (13.3.1.1.4), the defect selection procedure (13.3.1.1) canbe used to steer the defect-based ATPG process (13.3) to achieve itsgoals. The efficiency of the defect-based ATPG and the effectiveness ofthe test patterns typically depends on this procedure, which isexplained next.

One possible implementation for the defect selection method is asfollows (which is similar to the pattern selection method explainedearlier). Among the undetected faults, two classes C1, C2 are found withthe property defined by Equation I above. From each of these classes,the highest-ranking defect(s) are selected as the next target defects.This method is extendable to include three or even more classes todistinguish. For distinguishing defects, the ATPG typically has threebasic choices: not to control, not to observe, or to observe the effectson different observation points.

As shown in FIG. 22, ATPG (13.3.1.2) uses the target defect set and theATPG task (13.3.1.1.4). At first, faults can be selected from the defectenhanced fault list (A) that correspond to the selected defects of thetarget defect set (13.3.1.1.4). If there are multiple choices, the ATPGcan influence the success of the pattern generation at this stage bychoosing a particular set of faults. For example, assume the task is todistinguish between two bridge defects B1 and B2, connecting signallines X and Y, and X and Z, respectively. Further, assume the commonaggressor-victim mapping of a bridge defect into four stuck-at kinds offaults. Selecting as aggressor of B1 signal line Y being high and forbridge B2 signal line Z being high, both defects would propagate anidentical fault effect over signal line X, and are therefore likelyindistinguishable. (Signal lines Y and Z can still vary.) A betterchoice would be for the bridges to choose signal line X as theaggressor. Then, Y and Z do propagate the faulty effect. This means theeffect is propagated via a different path.

For the selected set of target faults, the ATPG (13.3.1.2.2) tries tosatisfy the task defined in target defect set and ATPG task(13.3.1.1.4). In case the task requires distinguishing between two ormore defects, the ATPG has several options. For example, it can blockthe fault effect propagation for some of them, allowing only the othersto be detected, or it can propagate the fault effect to differentobservation points. If successful, the ATPG procedure (13.3.1.2.2)computes a test pattern candidate (13.3.1.2.3), which, as shown in FIG.23, can be defect simulated (13.3.1.3). Note that this simulation isdifferent from regular fault simulation, since the fault simulator doesnot need to update the fault list (A) because it does not know yet ifthe pattern candidate (13.3.1.2.3) will be accepted for addition intothe test-pattern set. Therefore, in one implementation, the defectsimulation procedure (13.3.1.3) stores the simulated responses(13.3.1.3.1) of the candidate test pattern for later evaluation. Thisevaluation can be performed, for example, by the response analysisprocedure (13.3.1.4) shown in FIG. 24. At this point, it is alreadyknown that the pattern generation was at least in part a success.

Referring now to FIG. 24, the response analysis procedure (13.3.1.4) caninvestigate the effect the candidate test pattern has on all the otherdefects. It may determine, for example, that the disadvantages for otherdefects outweigh the advantages for the target defects, and thereforedismiss the candidate test pattern. The test goal verification procedure(13.3.1.4.1) uses the pattern candidate (13.3.1.2.3), its simulatedresponse (13.3.1.3.1), and the set of target defects and tasks(13.3.1.1.4). The test goal verification procedure (13.3.1.4.1) canfurther interface with the internal dictionary (B) and the previouslycomputed ranking. Based on this information, the test goal verificationprocedure (13.3.1.4.1) can determine whether the test pattern candidatecan be accepted. If yes, the test pattern candidate can be added toATPG's defect-based test pattern set (13.3.1.6). However, in eithercase, the defect-enhanced fault list (A) and the internal dictionary (B)can be updated as shown in FIG. 25 (especially with the informationlearned in the case the candidate test pattern was invalidated so thatthe next target defect-set selection can be improved).

FIG. 26 shows the optional pattern optimization procedure (13.3.2) thatcan succeed the ATPG. Typically, the optional defect-based test patternset (13.2.3) and the newly generated defect based test pattern set(13.3.1.6) together form the defect-based test pattern set (13.3.2.1),which can be improved by the optimization of defect-based test patternsprocedure (13.2.2) described earlier. Accordingly, in this exemplaryembodiment, the final test pattern set (13.3.3) in FIG. 13 is eitherdefect-based test pattern set (13.3.2.1) or the optimized defect-basedtest pattern set (13.3.2.2).

Test-Result Analysis/Diagnosis

During production testing of the integrated circuit, test patterns areapplied to the integrated circuits. After each application, the valuesat the observation points are compared with the expected values. Ifthere is a mismatch, the circuit fails the test. The test-result data istypically stored in a tester log, which can contain the indices offailing patterns, together with the observation points where themismatches have occurred (called failing bits). The tester log can beconfigured to contain a fixed number of failing patterns, or a fixednumber of failing bits, or all the failing patterns for each failingdevice.

FIG. 31 is a block diagram showing an exemplary manner of implementingthe test-result analysis component (21), wherein the test results arediagnosed and analyzed to identify one or more defect candidates thatpotentially caused any observed failures. The exemplary methodillustrated in FIG. 31 uses the production test result data (20) and thefault dictionary (16). The method identifies the defects that couldpossibly cause the failure and, in the exemplary embodiment, generates aranked list of defect candidates (sometimes referred to as the list ofsuspect features). Since each defect has an ID indicating which class itbelongs to, in the event that all candidates fall into the same class,the defect identification procedure can stop and proceed to analyze thefail data associated with the next integrated circuits. In this way, acorresponding pareto chart can be updated without precision loss.Otherwise, techniques including incremental simulation and diagnosis canbe employed to differentiate the matching candidates. If the candidatesare still indistinguishable, probabilistic measures can be assigned tothe classes to which the defects belong.

Defect Identification (21.1)

To identify defects, embodiments of the defect identification procedure(21.1) can retrieve from the fault dictionary (16) the faults associatedwith the failing bits of the observed failing patterns. The faults canbe matched with one or more defect candidates. Embodiments of the defectidentification procedure (21.1) can analyze the defects thus retrievedand generate a ranked list of matching defect candidates. Twononlimiting exemplary techniques for defect identification using a faultdictionary are presented below.

First Exemplary Technique for Defect Identification

The first exemplary technique operates using two processes: (1)identifying and ranking the defect candidates by analyzing the failingbits of individual failing pattern; and (2) out of the defect candidatesidentified and ranked, identifying and ranking those defect candidatesthat match the behaviors demonstrated by the analyzed failing patterns.These two exemplary processes are discussed in detail below.

1. Identify and Rank the Defect Candidates by Analyzing the Failing Bitsof Individual Failing Pattern

1.a Fault/Defect Classification

As described previously, the fault dictionary for purposes of thisdiscussion records only a limited number of failing responses for eachfault. Let this number be N. Therefore, when analyzing the fail dataassociated with each failing device, the exemplary method retrieves theentries associated with failing bits of the first N failing patterns.

Assume for these failing patterns V_(b) i=(1, 2, . . . , N that thenumber of failing bits is M_(i) and that for each of M_(i) bits, theassociated set of faults is F_(ij) (j=1, 2, . . . , M₁). Some faults canoccur in multiple sets. A measure f_(occ) can be assigned to each faultf to record the number of times f occurs in these M_(i) sets. Here,min{f_(occ)}=1, max{f_(occ)}=M_(i). In certain embodiments, the numberof observation points the fault f propagated to when simulating patternV_(i) can be recorded as f_(osim) in the fault dictionary. Based on thevalues of f_(occ), f_(osim) and M_(i), the fault setF_(i)=F_(i1)∪F_(i2)∪ . . . ∪F_(i,Mi) can be classified into four typesin this exemplary embodiment:

Type I: F_(I)={f:f_(occ)=f_(osim)=M_(i)}, which implies that thepredicted faulty behavior perfectly matches the observed behavior,

Type II: F_(II)={f:f_(occ)=f_(osim)<M_(i)}, which implies that theoutput errors predicted by the fault is the subset of observed outputerrors;

Type III: F_(III)={f:f_(occ)=M_(i)<f_(osim)}, which implies that theoutput errors predicted by the fault is the superset of observed outputerrors; and

Type IV: F_(IV)={f:f_(occ)<M_(i) and f_(occ)<f_(osim)}, which impliesthat the output errors predicted by the fault partly overlap withobserved output errors.

FIG. 33 illustrates four cases in which the predicted faulty behaviorsand the observed behavior have different relations. It can be shown thatFi=F_(I)+F_(II)+F_(III)+F_(IV).

The measures and classifications introduced above for faults can beconverted to the ones used for defects (e.g., using analogous numbersand sets d_(occ), d_(osim) and D_(l) (I=I, II, . . . , IV)). In general,there exist direct mapping relations from faults to defects, and eachfault in the fault dictionary will typically have an ID indicating whichdefect it represents. A defect could be modeled as a single fault ormultiple faults. In both cases, d_(occ), d_(osim) and D_(l) (l=I, II, .. . , IV) can be directly derived from f_(occ), f_(osim) and F_(l) (l=I,II, . . . , IV).

1.b. Individual Pattern Match

Type I defects should typically rank highest since they match theobserved behavior. Let the priority parameter assigned to type I defectsbe λ₁ (0<λ₁≦1). Typically, λ₁ is set to 1.

Two or more type II defects, however, might explain the observedbehavior. If a combined set of type II defects results in the samebehavior as observed, they should also rank high in the candidate list.Let the priority parameter assigned to these type II defects be λ₂.Typically, λ₂=λ₁. The exemplary method identifies the type II defectcandidates by way of solving a set cover problem, which can beformulated as follows:

Assuming the type II set consists of S defects, one variable x_(j)(x_(j)ε{0, 1}) can be created for each defect. According to oneimplementation, this variable will be 1 if the corresponding defect isselected as a candidate, and will be 0 otherwise.

{x_(j)} can be found such that

${2 \leq {\sum\limits_{j = 1}^{S}x_{j}} \leq \eta_{1}},$

subject to

${{\sum\limits_{j = 1}^{S}{A_{l,j}x_{j}}} \geq 1},$

(l=1, 2, . . . , M_(i)), A_(l,j)ε{0, 1}, where A is a M_(i)×S matrix.A_(l,j) will be 1 if defect j explains the error on the l-th output, andA_(l,j) will be 0 otherwise. The threshold η₁ is set to limit the numberof multiple defects candidates. For example, it could be viewed asunlikely that four or more defects exist and manifest themselves on theoutputs simultaneously under a particular pattern, so the threshold η₁can be set to three in some implementations. FIG. 34 shows an examplewhere the observed failing bits are the combination of the ones resultedby two different type II defects.

Type III defects represent those for which the behaviors are not fullycaptured by the fault model. For example, the Byzantine Generals Problemfor bridging faults, can cause errors to occur downstream from subsetsof fanouts of a bridged node. However, a typical 4-way bridging faultmodel used during simulation assumes that all fanouts of a bridged node(victim) take faulty values. Consequently, the errors introduced by the4-way bridging fault can be propagated to more circuit outputs thanwould be affected by the actual bridge defect. It should be clear thatthe unmodeled behavior can also affect diagnosis in other ways. Forexample, the unmodeled behavior can cause the errors introduced by thefault model to appear on fewer circuit outputs than would be affected bythe actual defect, or the error introduced by the fault model can bedetected by a test pattern that would never activate the defect. Ingeneral, type III defects can only cover a subset of unmodeled defects.Type III defects are possible candidates and the priority parameterassigned to them can be λ₃ (0<λ₃≦λ₂). Type IV defects are not consideredas candidates in this exemplary diagnostic method.

As a result of this first process of the defect identificationprocedure, a list of defect candidates and their associated quantitativemeasure of match goodness is generated for the first N failing patterns.The list for the failing pattern V_(i) (i=1, 2, . . . , N) can have thefollowing exemplary format:

D _(cond)(V _(i))={{d ₁,λ₁ },{d ₂,λ₁},{(d ₃ ,d ₄),λ₂ },{d ₅,λ₃}, . . .}.  (2)

2. Out of the Defect Candidates Produced by Process (1), Identify andRank Those that Match the Behaviors Demonstrated by all Analyzed FailingPatterns.

In the simplest case, simulation results of a single defect match theobserved behavior over the first N failing patterns. It is ordinarilytrivial to identify those kinds of defects by simply picking up thecommon elements of D_(cond)(V_(i)). However, this approach can fail ifthe circuit-under-test comprises multiple defects and each of thedefects manifests itself under different test patterns. It is alsopossible that the fault model is not accurate enough, and that theerrors predicted by the fault model do not match the observed behavior,thus resulting in a few unexplained test patterns.

The defects identification problem in process (2) can be formulated intothe following set cover problem:

Given the first N failing patterns V_(i) and the associated setsD_(cond)(V₁), the set D_(cond)(N) can be defined as

${\bigcup\limits_{i}{D_{cand}\left( V_{i} \right)}} = {\left\{ {\left\{ {d_{1},\lambda_{1}} \right\},\left\{ {d_{2},\lambda_{1}} \right\},\left\{ {\left\{ {d_{3},d_{4}} \right),\lambda_{2}} \right\},\ldots} \right\}.}$

A variable y_(m)(y_(m)ε{0, 1}) can be created for each element of theset D_(cond)(N). In one implementation, this variable will be 1 if thecorresponding defect(s) is selected as a candidate, and will be 0otherwise. Another variable k_(m) is created to indicate the size ofeach element in set D_(cond)(N). For example, the variable k_(m)associated with the element {(d₃, d₄), λ₂} is 2.

{y_(m)} can be found, such that

${1 \leq {\sum\limits_{m}{k_{m}y_{m}}} \leq \eta_{2}},$

subject to

${\sum\limits_{m}{B_{i,m}y_{m}}} \leq 1$

for (i=1, 2, . . . , N), B_(i,m)ε{0,1}, where B_(i,m) will be 1 if thetuple {d_(j), λ_(j)} corresponding to y_(m) is contained inD_(cond)(V_(i)) (i.e., {(d_(j),λ_(j)}εD_(cond)(V_(i))); B_(i,m) will be0 otherwise. The threshold η₂ can be set to limit the size of candidatespace. For example, η₂ can be set to three in one implementation,considering that the number of defects present in a circuit is unlikelyto be more than three.

FIG. 35 is an example showing that the observed failing behaviors can beexplained by the combined simulation results of multiple defects d₂ andd₃. The set of solutions to this set cover problem represents thosesingle defect or multiple defects that completely or partially match theobserved failing behavior. The defect candidates can be orderedaccording to their relative match goodness. The criteria for judging thematches can be based on two observations: (1) for an individual matchfor a particular failing pattern, the best candidates are the ones thatmatch observed output errors, followed by the ones that contain thelargest amount of the output errors. This is reflected by the parametersλ₁, λ₂, and λ₃, which were defined in the identification processdiscussed in the previous section; and (2) correct candidates usuallyexplain more numbers of failing patterns. To account for this, theparameter β_(i) (0<β_(i)<0.5) can be defined for each V_(i) (i=1, 2, . .. , N). λ and β can be combined to compute the quantitative measure ofmatch goodness for each defect candidate. The following pseudo-codeshows one exemplary manner in which the match measure y can be computedfor defect candidate d_(j):

1. γ←1;

2. loop i=1, 2, . . . , N

3. if {d_(j),λ_(j)}εD_(cond)(V_(i)) then γ←γ×λ_(j),

-   -   else γ←γ×β_(i);

4. end loop

One can see from the pseudo-code above that the larger γ is, the betterthe candidate matches the observed behaviors.

This exemplary identification procedure analyzes the first N failingpatterns because the fault dictionary stores up to N failing responsesfor each fault. If information is available to help analyze the rest ofthe failing patterns, higher diagnostic resolution can be achieved. Forexample, the fail log for a defective circuit contains No (N₀>N) failingpatterns. Defect a and b share the same fault signature over the first Nfailing patterns, hence they are indistinguishable and said to be in anequivalent class. However, if it is known that a results in N₀ failswhen the test set was simulated, and b only causes N fails, defect a canbe identified as the more likely candidate.

After the identification procedure, the defect candidate list and theassociated match goodness measures can be calibrated by the informationmentioned above. A table can be created while simulating the test set torecord for each defect the number of times it was detected by the giventest set. For example, suppose the fail log contains N₀ (N₀>N) failingpatterns for a defective circuit. If, as shown in the table, a defectcandidate d_(j) fails n_(dj) times, and n_(df)<N₀−N_(th) (N_(th) is apredetermined threshold and N_(th)>0), the associated match qualitymeasure can be adjusted, for instance γ←γ×δ (0<δ<1). As a result, theexemplary diagnostic method can keep in the final list Q highest rankedcandidates for which γ>γ_(th) and where Q is a predetermined limit. Ifthese Q candidates comprise candidates that are not from the same class,techniques such as incremental simulation and incremental diagnosis canbe employed to differentiate the candidates. Alternatively, theexemplary procedure can assign likelihood credits to the involvedclasses based on the match goodness measure of the defect candidates andother probabilistic measures associated with the defects. Depending onthe configuration of the diagnostic system, the incremental simulationand incremental diagnosis can be invoked whenever the two-step procedurefails to identify which defect class explains the observed behavior, orwhen deemed necessary by the diagnostic system after a certain number ofdefective integrated circuits occurred without successfully identifyingthe defect class.

Second Exemplary Technique for Defect Identification

This section discusses the second exemplary technique for defectidentification, which proceeds with a discussion of how the faultdictionary can be created, followed by a discussion of how informationcan be retrieved from the dictionary.

1. Creating the Fault Dictionary

Conventional fault dictionaries (or thesauruses) are typically too largeto be loaded in a physical memory for modern multi-million designs, orare too inefficient to access due to the encoding techniques adopted. Inthis section, embodiments of a compressed dictionary scheme aredescribed that enable the storage of a large amount of fault detectinginformation and allow for efficient access of the stored fault detectinginformation during test-result processing. Using embodiments of thedisclosed scheme, a large volume of production test results can bequickly processed and the defectivity mechanism information derived.

For illustrative purposes, this discussion makes reference to FIG. 46,which shows an exemplary fanout-free region embedded in a circuit. Theexemplary region comprises one NAND gate and one OR gate. Signal s istermed the “stem” of this fanout-free region, and signal lines a, b, c,and d are internal signals. For illustrative purposes only, assume thatonly combinational test pattern sets are used to test this circuit. Thisassumption should not be construed as limiting, however, as thedescribed methodology can be readily adapted by one of skill in the artfor use with other types of test patterns.

A single fault can typically be detected by many different testpatterns. Further, the observation point combinations for a specificfault produced by different detecting test patterns are often highlysimilar due to structural constraints of the circuit logic. For example,the number of unique observation point combinations for a given fault istypically small, and the total number of detecting test patterns for afault could be much higher because many faults are random-testable.Therefore, according to one embodiment, the size of the fault dictionarycan be reduced by assigning one unique ID for each unique observationpoint combination. When the detecting test responses for a fault arestored, instead of listing all observation points for every detectingtest pattern, the unique ID for the corresponding observation pointcombination is used to reduce the memory usage. This technique can beespecially effective for frequently used observation point combinationshaving many observation points because the memory cost for anobservation point combination is gradually reduced over many detectingtest patterns and many faults.

For example, if fault a stuck-at-1 is detected by a test pattern p atsome observation points, then fault s stuck-at-0 is also detected at thesame list of observation points. This is also true of internal fault cstuck-at-1 and stem fault s stuck-at-1. Based on this observation, thesize of the fault dictionary can be further reduced by only storing thefull detecting test responses for stem fault s stuck-at-0 and stemfaults stuck-at-1. For the other one or more faults associated with theinternal signals of this fanout-free region, only the detecting testpatterns need to be stored, and the observation point information can berecovered from either fault s stuck-at-0 or fault s stuck-at-1. Further,in one exemplary implementation, at least some of the detecting testpatterns for stem faults are put into a list, and a bit mask is used forevery non-stem fault to store the detecting pattern information.

This technique can also be applied to the extracted defects (forexample, opens and bridges). For instance, assume that there is an opendefection signal line din FIG. 46. For illustrative purposes, assumethat this open defect is a complete open. The voltage of the input pinof OR gate connected with d thus becomes floating and can be determinedby many factors, such as residual charges, capacitive coupling withphysical neighbors, and the voltage of physical neighbors. Typically,the open defect is modeled as a stuck-at-X fault, which means that itcan manifest itself as fault d stuck-at-0 under certain test patternsand as fault d stuck-at-1 under others. Because the detecting testresponses of fault d stuck-at-0 and fault d stuck-at-1 are subsets ofstem fault's stuck-at-0 and stem fault s stuck-at-1, respectively, a bitmask can be used to effectively capture the detecting test responses forthis open defect by using the detecting test responses of stem faults asthe basis.

Consider further a bridge defect between signal line c and g. Assumethat this bridge defect behaves like a dominant-type bridge, where g isthe aggressor and c is the victim. Statically this bridge is activatedwhen the signal line c and g have the opposite logic values, the bridgewill behave-like fault c stuck-at-0 when g is “0” or like fault cstuck-at-1 when g is “1.” Similar to the previous open defect discussed,in order to store the detecting test responses for this bridge, only afew bits are needed to indicate which pattern can detect this bridgedefect, and the detailed detecting observation points can be recoveredby referring to the complete detecting test responses of stem faults sstuck-at-0 and s stuck-at-1.

A fault dictionary typically contains a lot of information redundancyamong the various faults and defects in the fault dictionary. Accordingto particular embodiments of the disclosed technology, a faultdictionary can be created that uses one or more bit masks and/or uniqueIDs to replace the direct description of detecting test responses. Theinformation redundancy and the final size of fault dictionary cantherefore be substantially reduced. In order to achieve the desirablyfast accessing during test-result processing, the complete faultdictionary can be organized into a dedicated hierarchical architecture.Thus, complicated and time-intensive encoding methods (such as Huffmancoding and LZW encoding) can be avoided.

In one specific exemplary implementation, the compressed dictionary isconstructed as follows: One or more possible observation pointcombinations for the targeted faults (for example, all observation pointcombinations) and defects (for example, all defects) are identified fora selected integrated circuit design and put into a group of observationpoint combinations (sometimes referred to as the observation pointcombination pool). Each of the observation point combinations can thenbe assigned an ID (for example, a unique ID) for future reference. Inorder to provide for more efficient access, the observation pointcombinations can be hashed. For example, the IDs of observation pointscontained in each observation point combination can be used to computethe hash key. The detecting test responses can be collected for a listof so-called “pseudo faults,” which refer to those faults used as abasis for other faults and defects. One possible way of collecting testresponses for pseudo faults is based on using stem stuck-at-X faults forone or more fanout-free regions in the design (for example, everyfanout-free region). For a given fanout-free region, the stem stuck-at-Xfault can be simulated and the detecting test responses are stored (forexample, as a list of detecting test patterns). In this exemplaryimplementation, a pair of IDs is used for each detecting test pattern.For instance, the first ID can represent (or indicate) the test pattern,and the second ID can refer to the observation point combination in thepool established above. The list of pseudo faults can additionally besorted for faster access. For example, all pseudo faults can be sortedbased on IDs of the corresponding fanout-free region, which allows us toquickly find the pseudo fault for a given fanout-free region by usingbinary search. These acts can be performed to create the basis of thecompressed dictionary. After the basis is created (or as it is beingcreated), the detecting test responses of one or more other faults ordefects can be compressed into a bit mask based on the correspondingpseudo fault. For example, for a given fault f, a bit mask with a lengthcorresponding to the number of de test patterns of its correspondingpseudo fault of can be used to compress the detecting test responses. Inuse, if f is detected by a test pattern in the same way as of thecorresponding bit in the bit mask is set; otherwise, that bit is reset(or vice versa depending on the implementation).

For most faults and defects, the corresponding detecting test responsescan be compressed into bit masks, and accordingly the size of the faultdictionary is reduced. In situations where embodiments of the describedcompression technique do not work (for example, if internal fault f isdetected in a way different from its stem fault by a given test pattern)a separate entry can be created and used to describe this detectingpattern for f based on a pair of pattern IDs and observation pointcombination IDs. Further, one or more of the faults associated with thesame pseudo fault can be arranged as neighbors within the whole faultlist in order to enable more efficient access during test-resultprocessing.

The above-described embodiments should not be construed as limiting inany way, as alternative or supplemental techniques can be performed inorder to realize other desirable features or improvements of faultdictionary compression. For example, based on the observation that thereexist many similarities among the observation point combinationsdetermined, the memory requirement for the observation point combinationpool can be further reduced by incrementally describing one or more ofthe observation point combinations from the group of observation pointcombinations. For instance, in certain embodiments, only the differencesfrom the base observation point combination are stored for eachobservation point combination. Another possible embodiment reduces thenumber of pseudo faults (and thus the memory used to store the detectingtest responses for pseudo faults). For example, instead of creating apseudo fault for each fanout-free region, two or more fanout-freeregions (for example, closely related fanout-free regions) can becombined and a single pseudo fault created for faults within thecombined region.

Further, in architectures where an output response compactor is used,embodiments of the exemplary dictionary compression schemes describedabove can also be used. For example, the compacted detecting testresponses can be stored into a fault dictionary using the proposedtechniques and directly used for test-result processing without havingto recover the original test responses before compaction. Further, itshould be understood that the exemplary embodiments of the compressiontechnique are described as applying to static faults and defects forillustrative purposes only. The techniques can also be applied totiming-related, dynamic faults and defects. For example, when an speedtest pattern set is applied, the detecting test responses can becomputed for transition faults and timing-related defects. Observationpoint combinations can be computed for all transition faults and putinto the group of observation point combinations (for example, theobservation point combinations pool). The detecting test responses ofpseudo faults can be computed, for example, for each fanout-free regionbased on a stem's slow-to-rise fault and slow-to-fall fault. Othertransition faults and timing-related faults can be compressed into a bitmask, whenever possible, using the corresponding pseudo fault as thetemplate. For a test pattern set with both static and at-speed testpatterns, two fault dictionaries can be created separately for staticand timing-related faults and defects. In one embodiment, these twofault dictionaries are sequentially accessed during test-resultanalysis.

2. Retrieval of Information from Dictionary

During test-result processing, the compressed dictionary allowsefficient retrieval of the stored detecting test responses for faultsand extracted defects and fast diagnosis for failing integratedcircuits, providing the high throughput required for analyzing volumeproduction test. During diagnosis, every failing test pattern of afailing integrated circuit is individually analyzed. For a given failingtest pattern, all suspects which can explain this failing test patternare identified by the following procedure: the ID for the observationpoint combination of the current failing test pattern is firstdetermined by searching the observation point combination pool; then allpseudo faults which can explain this test pattern are identified bycomparing the ID of the failing test pattern and the ID of theobservation point combination of the failing test pattern. The suspectlist for this failing test pattern can be identified by checking the bitmask of all faults and defects associated with the pseudo faultsdetermined above. This procedure can be repeated for all failing testpatterns. In the end, a list of suspects is determined, each explainingat least one failing test pattern. This list can be further processed togenerate a list of potential defects (or defect candidates), which couldexplain all or at least a majority of the failing test patterns andalso, optionally, the passing test patterns. Further, the list ofpotential defects can include additional information related to thepotential defects identified. For example, one or more of the followingproperties can be further associated with the potential defects in thelist of potential defects: (a) a defect identifier that distinguishesthe respective potential defect from, other potential defects, (b) aderived rule identifier that identifies the defect extraction rule usedto extract the respective potential defect; (c) a design manufacturingrule identifier that identifies the design manufacturing rule from whichthe defect extraction rule used to extract the respective potentialdefect was derived; (d) a physical location of the respective potentialdefect in the physical layout of the integrated circuit design; (e)physical properties of the respective potential defect in the physicallayout of the integrated circuit design; and (f) a ranking of therespective potential defect relative to other potential defects.

Incremental Simulation (21.2)

The fail log for a defective circuit can contain failing patterns notanalyzed by the defect identification procedure (21.1). An incrementalsimulation procedure (21.2) can be used to simulate one or more of thesefailing patterns. According to one exemplary embodiment, the defects tobe simulated are selected from the ranked candidate list. Further, thesame fault models as used in the fault dictionary computation processcan be applied to defects under consideration. If none of faultsrepresenting a defect match the observed failing behavior (the criterionfor judging match-goodness can be similar as what were defined for typeI, II and m defects in the defect identification process (21.1)), thedefect can be dropped out of the candidate lists. The incrementalsimulation can stop once the defects remaining in the candidate listfall into one class, since the failing mechanism can be uniquelyidentified.

Incremental Diagnostics (21.3)

It is possible that none of the defects in the fault dictionary are ableto explain the observed failing behavior. The reasons could be, forexample: (1) the faults modeling the defects are not accurate enough,and are thus unable to fully capture the behavior of the defect undersome test patterns; or (2) the defect(s) being diagnosed were notconsidered as potential candidates during the defect-extraction stage.Therefore, the fault signatures of the defects may not be stored in thefault dictionary.

According to one exemplary embodiment, incremental diagnostics (21.3)can be used to analyze the observed failing behaviors if the defectidentification procedure (21.1) and the incremental simulation (21.2)generate an empty candidate list. Incremental diagnostics (21.3) can beperformed, for example, by the advanced diagnostics component (4726)shown in FIG. 47. For example, an effect-cause-based diagnosticprocedure can be used to analyze the actual responses and determinewhich defect(s) potentially caused the observed behavior. Theincremental diagnostic procedure (21.3) typically produces a list ofcandidates as well as the associated fault types. If the candidates fallinto the same, class, yield loss pareto charts can be updated withoutresolution loss. Otherwise, probabilistic measures can be assigned tothe classes these candidates belong to.

The defect candidates can be stored in a separate file, which can beused later for the purpose of learning of new defect rules. Also, thedefect dictionary can be updated by incorporating data about thesedefect candidates.

Graphical Representation Computation (21) (22)

One or more graphical representations of the diagnostic results (21.4)can be computed using a graphical representation computation procedure(22) as shown in FIG. 31. The graphical representation computationprocedure (22) corresponds to the diagnostic results analysis component(4718) shown in FIG. 47. One exemplary representation that can becomputed using the diagnostic data is a pareto chart Accordingly, theremainder of this section will discuss the generation of a pareto chart,though it should be understood that other graphical representationsindicating the likelihood of potential defects in the integrated circuitcan alternatively be computed.

Pareto chart computation involves the computation of fail probabilitiesof the various yield limiting features in the design. For purposes ofthis discussion, the term “features” refers to those characteristics ina design that are prone to failure during manufacturing, and thereforeat least partially contribute to yield loss. The physical instantiationof a feature can range from very specific elements (for example, twometal lines that run parallel to each other at minimum spacing for along distance and thus are prone to bridging) to more general elements(for example, all nets, or library cells in the design). In thissection, features are denoted as f₁, f₂, . . . f_(K). For a givendesign, each feature can have multiple instances (for example, a singlevia is a feature that is prone to being malformed leading to opens, and,in a design, there can be millions of single via instances). Theinstances of a feature f_(i) are denoted as f_(i) ¹, f_(i) ², . . .f_(i) ^(n) ^(i) , where n_(i) is the number of instances of f_(i) in thedesign. During manufacturing, each feature can potentially be malformed.As used herein, the probability of this happening is denoted by p_(foil)(f_(i)). In certain embodiments of the disclosed technology, the objectof the pareto chart computation is to estimate these probabilities offailure for different features from the high volume of the diagnosticresults gathered during production.

If diagnosis were ideal (for example, for each failing die, diagnosiswas able to pin-point the exact cause of failure), estimating the failprobabilities would be simplified: the fail probability would be theratio of the number of times a feature failed to the number of times afeature was manufactured. However, in reality, diagnosis is not always100% accurate. Usually, diagnosis (such as the test-result analysis(4716) shown in FIG. 47) produces a list of suspect features that arelikely to be the cause of the failure in a defective die instead of theactual failing feature(s). This is usually because, more often than not,failures in other features can equally explain the behavior of thedefective die observed on the tester. Accordingly, using only booleanvalue fail information, it can be difficult or impossible to distinguishamong certain features as the real cause of defect. As an example,consider the situation illustrated in FIG. 40 where there are multiplefeatures associated with the same net pair, such as a corner-to-cornerand a side-to-side bridge. In this case, it is typically not possible todetermine which is the real cause of a bridge on the net pair using onlylogic level diagnosis. Other causes of ambiguity in diagnosis areso-called “equivalent faults,” which are indistinguishable at the logiclevel. As an example, consider the exemplary buffer illustrated in FIG.41. The faults on the input and output of a buffer are equivalent Thismakes the task of estimating the fail probabilities of features anon-trivial one. To summarize, diagnosis of a multiplicity of failed dieproduces a list of suspect features that can potentially be the cause offailure for each die is provided. As an example:

Failed Die Number Suspect Features 1 f₃ ¹⁰⁰, f₁₀ ¹⁴¹, f₁₁ ¹¹⁵, f₃ ¹⁰¹ 2f₂ ¹³²¹¹, f₂ ¹³²¹³, f₆ ¹¹¹, f₆ ¹¹², f₆ ¹¹⁴ 3 f₇ ¹²³, f₇ ¹⁶⁵³ . . . . . .

According to one embodiment, pareto chart computation involves analyzingthe list of suspect features (such as the example above) to computereliable estimates of the individual feature fail probabilities:p_(foil) (f_(i)).

In the following section, two exemplary methods for computing individualfeature fail probabilities are described. These exemplary methods shouldnot be construed as limiting, however, as multiple additional oralternative methods can be used in any embodiment of the disclosedtechnology. In the first exemplary method, an iterative procedure isused to compute feature fail rates. In the second exemplary method, alinear-regression-based method that is based on partitioning the designinto smaller blocks and relating the fail rate of each block to thefeatures contained within the block is used. After the two exemplarymethods are described, the possible problem of bias introduced bywafer-level systematic defect causes is addressed. Such defect causescan affect die in certain areas on the wafer and possibly in specificregions within the die. Due to the non-random nature of such defects,such defect causes can introduce erroneous biases toward certainfeatures. An exemplary technique for addressing these effects is alsodescribed below.

1. An Exemplary Iterative Learning Procedure

In certain exemplary embodiments, an iterative learning procedure isused. In some implementations, the iterative learning procedurecomprises determining what the probability is that a particular featurein the list of suspect features is the actual cause of failure for agiven list of diagnosed suspect feature instances. This probability canbe described in terms of the unknown variables: p_(foil) (f_(i)). Theprocedure further comprises using this probability to estimate p_(foil)(f_(i)) itself. This creates a system of equations which can be solvedin an iterative fashion to estimate the fail rate of each feature.

Consider a defective die for which diagnosis produces the followingsuspect feature instances: f₂ ¹²³, f₃ ²², f₃ ²³, f₁ ¹⁰⁰¹. It is firstassumed that the actual failing feature instance(s) in the die is inthis list of suspect feature instances. The probability that, given theabove diagnosis results, the actual cause of defect in the die is f₂ ¹²³can be determined using probability theory by defining two events A andB as:

-   -   A=f₂ ¹²³ is the only cause of defect in a faulty die; and

-   B=At least one of the feature instances f₂ ¹²³, f₃ ²², f₃ ²³, f₁    ¹⁰⁰¹ is the cause of defect in a faulty die    The conditional probability of A given B is then:

$\begin{matrix}{{P\left( {A/B} \right)} = {\frac{P(A)}{P\left( {A\bigcap B} \right)} = \frac{P(A)}{P(B)}}} & (3)\end{matrix}$

since A⊂B. Now, assuming that all features fail independently, theprobability of events A and B can be given by:

$\begin{matrix}{\mspace{79mu} {{{P(A)} = {\frac{p_{fail}\left( f_{2} \right)}{\left( {1 - {p_{fail}\left( f_{2} \right)}} \right)}{\prod\limits_{i = 1}^{K}\; \left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{n_{i}}}}}\mspace{79mu} {and}}} & (4) \\{{P(B)} = {\frac{1 - {\left( {1 - {p_{fail}\left( f_{2} \right)}} \right)\left( {1 - {p_{fail}\left( f_{3} \right)}} \right)^{2}\left( {1 - {p_{fail}\left( f_{1} \right)}} \right)}}{\left( {1 - {p_{fail}\left( f_{2} \right)}} \right)\left( {1 - {p_{fail}\left( f_{3} \right)}} \right)^{2}\left( {1 - {p_{fail}\left( f_{1} \right)}} \right)}{\prod\limits_{i = 1}^{K}\; \left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{n_{i}}}}} & (5)\end{matrix}$

By substituting equations (4) and (5) into equation (3), the conditionalprobability becomes:

$\begin{matrix}{{P\left( {A/B} \right)} = \frac{{p_{fail}\left( f_{2} \right)}\left( {1 - {p_{fail}\left( f_{3} \right)}} \right)^{2}\left( {1 - {p_{fail}\left( f_{1} \right)}} \right)}{1 - {\left( {1 - {p_{fail}\left( f_{2} \right)}} \right)\left( {1 - {p_{fail}\left( f_{3} \right)}} \right)^{2}\left( {1 - {p_{fail}\left( f_{1} \right)}} \right)}}} & (6)\end{matrix}$

Now, the individual feature fail probabilities can be expected to be ofthe order of 10⁻⁸, otherwise almost every manufactured die will havemultiple failures and the yield will be almost be zero. Under thisassumption, the higher order terms in Equation (6) like p_(foil)(f_(i))², p_(foil) (f_(i))³, p_(foil)(f_(t)) p_(foil) (f_(j)) and so onwill be much smaller than the first order terms, and hence can beignored. With this simplification Equation (6);becomes:

$\begin{matrix}{{P\left( {A/B} \right)} \approx {\frac{p_{fail}\left( f_{2} \right)}{{p_{fail}\left( f_{2} \right)} + {2{p_{fail}\left( f_{3} \right)}} + {p_{fail}\left( f_{1} \right)}}.}} & (7)\end{matrix}$

In general, for a failed die with the following feature suspect listdetermined by diagnosis:

-   -   x₁ instances of f₁,    -   x₂ instances of f₂,    -   . . .    -   x_(κ) instances of f_(κ),        the probability that the actual cause of defect in the failing        die is an instance of f_(i) can be given by:        P(An instance of f_(i) is the actual cause of defect/Diagnosis        Results)

$\begin{matrix}{\approx \frac{x_{i}{p_{fail}\left( f_{i} \right)}}{\sum\limits_{j = 1}^{K}{x_{j}{p_{fail}\left( f_{j} \right)}}}} & (8)\end{matrix}$

Next, Equation (8) can be used to develop an estimator for p_(foil)(f_(i)). Consider again the earlier example where the list of diagnosedsuspects in a failed die is f₂ ¹²³, f₃ ²², f₃ ²³, f₁ ¹⁰⁰¹. So, in thiscase, there is one suspect instance each of features f₁ and f₂, and, twosuspect instances of feature f₃. Now, assume for illustrative purposesthat there are N_(similar) other failing die that have a similardiagnosis suspect list. That is, the suspect list contains one instanceeach of f₁ and f₂ and two instances of f₃. So, on an average out of theN_(similar) failing die, the number of die for which the real cause offailure is an instance of feature f₂ is given by:

N_(similar)P (An instance of f₂ is the actual cause of defect/DiagnosisResults)

$\begin{matrix}{\approx {\frac{N_{similar}{p_{fail}\left( f_{2} \right)}}{{p_{fail}\left( f_{2} \right)} + {2{p_{fail}\left( f_{3} \right)}} + {p_{fail}\left( f_{1} \right)}}.}} & (9)\end{matrix}$

From this example it can be seen that the failed die in the aboveexample contributes:

P (An instance of f₂ is the actual cause of defect/Diagnosis Results) tothe fail count of feature f₂ in the overall set of failed die. In otherwords, given a set of failed die, a die with a diagnosis suspect listthat has x_(i) instances of f_(i) will contribute (from Equation (8)):

$\begin{matrix}\frac{x_{i}{p_{fail}\left( f_{i} \right)}}{\sum\limits_{j = 1}^{K}\; {x_{j}{p_{fail}\left( f_{j} \right)}}} & (10)\end{matrix}$

to the feature fail count for f_(i). The contribution of each failed dieto the fail count of f_(i), as given by the above expression, can beadded and the sum divided by n_(i)N_(manuf) to get an estimate ofp_(foil) (f_(i)).

To summarize the exemplary technique, assume that there are N_(manuf)fabricated die. Assume further that out of these, N_(foil) are found tobe defective and are diagnosed. Let x_(i) ^(i) denote the number ofinstances of feature f_(i) in the suspect list for failed diel(1≦l≦N_(foil)). The fail rate for feature f_(i) can then be estimatedaccording to this exemplary embodiment as:

$\begin{matrix}{{p_{fail}\left( f_{i} \right)} = {{\frac{1}{n_{i}N_{manuf}}{\sum\limits_{l = 1}^{N_{fail}}\; {\left( \frac{x_{i}^{l}{p_{fail}\left( f_{i} \right)}}{\sum\limits_{j = 1}^{K}\; {x_{j}^{l}{p_{fail}\left( f_{j} \right)}}} \right)\mspace{14mu} {for}\mspace{14mu} 1}}} \leq i \leq K}} & (11)\end{matrix}$

Hence, there exists a system of non-linear equations in the unknownvariables, p_(foil) (f₁), and the known diagnosis results. Theseequations can be solved in an iterative fashion, starting from someinitial guesses of the p_(foil) (f_(i)) values and iterativelyconverging towards a solution. This exemplary technique can thus becharacterized as an iterative feature fail rate learning procedure andcan be used in connection with any of the disclosed embodiments.

2. An Exemplary Procedure for using Linear Regression on Design Blocks

In this section, another exemplary method of estimating feature failrates from the diagnostic results is described. The exemplary methodbuilds on top of the iterative procedure described in the previoussection.

In this exemplary method, the entire circuit design is partitioned intoB similar sized blocks. Each block can be characterized as a “smallerdie,” which contains a subset of the feature instances in the design.Due to natural variations in the design, the distribution of featureinstances is likely to vary from block to block. For example considertwo features: f₁=a single via between metal layer 3 and 4, and, f₂=asingle via between metal layer 1 and 2. One section of the design cancontain more instances of f₁ than f₂, while a different section can havemore f₂ instances as compared to those of f₁. Different design blockscan therefore have distinct characteristics. Thus, by relating the failrate of the design blocks to the feature instances in the block, aregression model with p_(foil) (f_(i)) as predictor variables and blockfail rates as observed variables can be constructed. The fail rate offeatures can then be estimated using standard regression techniques.See, e.g., N. Draper and H. Smith, Applied Regression Analysis(Wiley-Interscience 1998). The fail rate of each design block can alsobe determined from the diagnostic results using an embodiment of theiterative procedure described in the previous section. There are atleast two possible advantages of determining the feature failprobabilities in this fashion. First, half of the blocks in the designcan be used to train the regression model to estimate p_(foil) (f_(i)).These estimates can be validated by using them to predict the fail ratesof the remaining half blocks and by comparing them to the measured failrates from diagnostic results. Thus, this method can be characterized ashaving a built-in mechanism for validating results. Second, the use ofregression allows diagnosis errors to be tolerated (for example,diagnosis errors in which the feature instance that is the actual causeof failure in a defective die is not included in the diagnosis suspectlist). Assuming, for instance, that diagnosis errors are distributeduniformly over the design blocks, the errors will typically besubstantially averaged out during regression.

2.1 Partitioning the Design into Block Based on Nets

A design can be partitioned into blocks in many possible ways. Becausemost features can be associated with nets in the design, one exemplarytechnique partitions the design based on the nets. For instance, let NETbe the set of all nets in the design. If this set is divided into Bsubsets, NET₈, 1≦s≦B, the subsets will generally define different designblocks. According to one exemplary embodiment of the technique, themanner in which NET can be divided into subsets can be arbitrarilychosen. The resulting subsets, however, should desirably meet thecriteria mentioned above that the features in the subsets be diverse. Inaddition, the subsets are desirably not too small. Otherwise, theestimates of p_(foil) (f) can become statistically unreliable.

One exemplary manner for choosing the subsets is based on the scan cellsat which the stuck-at faults associated with a net are observed for agiven test pattern set. More specifically, the scan cells in the designare first grouped into B groups. This grouping of scan cells can bebased on the scan chains in the design (for example, scan cells adjacentto each other in a scan chain can be put in the same group). For eachstuck-at fault in the design, the observation scan cells can bedetermined using fault simulation. A net can then be placed into asubset based on what scan cell groups the stuck-at faults associatedwith the net are observed at. As an example, consider the exemplarydesign shown in FIG. 42. For exemplary purposes only, the exemplarydesign has only one scan chain Assume that the design is desirablyportioned into two blocks. To achieve this, the set of nets NET can bedivided into two subsets: NET₁ and NET₂. The scan cells can then begrouped into two groups, G₁ and G₂, as shown in FIG. 42. Consideringfirst the example net net_(a), it can be observed that the four faultsassociated with it (A stuck-at-1, A stuck-at-0, B stuck-at-1, and Bstuck-at-0) are observed at scan cells in group G₁. Consequently, thisnet can be included in NET₁. Note that for some nets, the faultsassociated with it may be observed in multiple scan cell groups. Forexample net_(e) is such a net since the faults C stuck-at-0 and Cstuck-at-1 are observed in scan cell group G₁ while the faults Dstuck-at-0 and D stuck-at-1 are observed in G₂. According to oneexemplary implementation, such nets can be arbitrarily placed into anyone of the subsets.

2.2 Determining Block Fail Rates and Relating them to Features

Once the design has been partitioned into blocks, the fail rate for eachblock can be determined from the diagnostic results. One exemplarytechnique for determining the fail rate is as follows. A list of suspectdesign blocks (or subsets NET₈) is determined from the list of diagnosedsuspect nets. The fail probabilities for these blocks are estimatedusing an iterative procedure (for example, the iterative proceduredescribed above in subsection (1)). For purposes of this discussion, letthese fail rates be denoted as {circumflex over (p)}_(foil)(NET_(s)).The estimated block fail rates can then be related to the feature failrates. For example, because a feature instance can be associated withone or more nets (a single net in the case of features like single vias,or two nets in the case of features like bridges), the feature instancesassociated with a subset NET_(s) can be determined. For example, lety_(is) be the number of instances of feature f_(i) associated withsubset NET_(s). The probability that there will be a defect in thesubset of nets NET_(s) can then be given by:

P(At least one feature associated with NET_(s), fails)=1−P(None of thefeatures associated with NET_(s), fails)

or, equivalently:

$\begin{matrix}{{{{\hat{p}}_{fail}\left( {NET}_{s} \right)} = {{1 - {\prod\limits_{i = 0}^{K}\; {\left( {1 - {p_{fail}\left( f_{i} \right)}} \right)y_{is}}}} \approx {\sum\limits_{i = 0}^{K}\; {y_{is} {p_{fail}\left( f_{i} \right)}}}}}\mspace{14mu} {for}{1 \leq s \leq B}} & (12)\end{matrix}$

Again, the above approximation can be justified by the observation thatthe values of p_(foil) (f_(t)) are expected to be much less than 1. Thesystem of equations in Equation (12) above define a linear regressionmodel with p_(foil) (f_(t)) as the predictor variables and {circumflexover (p)}_(foil)(NET_(s)) as the observed variables. This model can beused to generate estimates of p_(foil) (f_(i)) using well knownregression techniques (for example, a least squares estimationtechnique). See, e.g., N. Draper and H. Smith, Applied RegressionAnalysis (Wiley-Interscience 1998).

3. Hierarchical Yield Learning

There are certain defect mechanisms that affect die in only a certainarea of the wafer. For example, depth-of-focus-related problems may onlycause defects in die on the outer edges of the wafer. An example of suchproblems is shown in FIG. 43. Further, stepper-related issues may onlyshow up in every fourth die on the wafer. Such systematic defectmechanisms have the potential to wrongly bias the fail rates of featuressince they do not affect all die uniformly. As an example, consider asituation where the die on the periphery of some wafer have anout-of-focus issue that causes a particular net in the design to bridgewith another net. Further, assume that there is a corner-to-cornerbridge feature associated with this net pair. Since a large number ofdie on the wafer periphery may exhibit this systematic defect mechanism,it could be perceived that the fail rate of corner-to-corner bridges ishigh. However, this perception would be incorrect because die in theinterior of the wafer will not be affected by the out-of-focus problem,and hence the corresponding die will not exhibit a high corner-to-cornerbridge fail rate. In order to alleviate this problem, and according toone exemplary embodiment, a hierarchical yield learning procedure can beused. In one example implementation of the procedure, failing die thatfail due to a location-on-wafer-specific defect mechanism areidentified. These die are then excluded from fail rate computation, thusavoiding the error introduced by systematic issues that do not affectall the dies uniformly.

In some cases, the wafer-location-specific defect mechanisms are veryprominent. Such cases could be identified, for example, from a waferdefect map, which shows the location of defective die on the wafer. Anexample of a wafer defect map is shown in FIG. 44. However, in othercases, the systematic issue can become disguised by the regularlyfailing die. The use of diagnostic results in uncovering such issuesthat are hard to identify from simple wafer defect maps can bebeneficial. As an example; consider a case where a wafer-levelsystematic mechanism causes a defect in a specific net (for example,net_(a)) in only those die that are located at four specific locationson the wafer (for example, as shown in FIG. 45). This subtle mechanismwill not be easy to identify from the wafer defect map (FIG. 44).However, the mechanism can be uncovered by determining so-called “hotnets” using the diagnostic results. Generally speaking, hot nets can becharacterized as those nets that fail at a rate disproportionatelyhigher than other similar nets. In the illustrated example, net_(a) willbe designated as the hot net. Hot nets in failing die can be identifiedby letting the features be individual nets and then using the iterativelearning procedure to determine net fail rates. Those nets whose failrates are higher than some threshold can accordingly be categorized ashot nets. One exemplary threshold value can be the expected fail rate ofa net. This can be estimated from the fail rates of features associatedwith the net. Thus, if a net fails more often than expected, it can becharacterized as a hot net. Once hot nets are identified, for instance,the wafer defect map can be updated to show only those failing die thatcontain the hot net. The resulting map will consequently be indicativeof the systematic issue (as shown, for example, in FIG. 45). A so-called“wafer map visualization rule” can be used to denote the criteria forchoosing failed die to depict on the wafer map. Other examples of typesor categories of wafer map visualization rules (besides hot nets)include, but are not limited to: die that have failures in certaincells, die that have failures in certain metal layers, or other rulesthat the user of this technique wishes to define. The describedvisualization schemes are made possible by the use of high volumein-production-diagnosis.

4. Estimation of Test Escape Rate

Some defective manufactured integrated circuits may not be identifiedduring testing because the test set may not detect the failing featureinstances in the defective die. Such die are referred to as testescapes, and it is often desirable to estimate the test escape rate fora particular test set. This can be done in some embodiments of thedisclosed technology using the feature fail probabilities determinedfrom volume diagnosis results as described in the previous subsectionsusing the following exemplary procedure. In general, the test escaperate is the probability that at least one untested feature instancefails while all the feature instances detected by the test set do notfail. Let u_(i) be number of instances of feature f_(i) that are notcovered by test. This number can be determined using fault simulation ofthe test set. Then the probability of test escape is given by:

$\begin{matrix}{p_{escape} = {{\left( {\prod\limits_{i = 1}^{K}\; \left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{({n_{i} - u_{i}})}} \right)\left( {1 - {\prod\limits_{i = 1}^{K}\left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{u_{i}}}} \right)}\mspace{70mu} = {\prod\limits_{i = 1}^{K}{\left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{n_{i}}\left( \frac{1 - {\prod\limits_{i = 1}^{K}\left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{u_{i}}}}{\prod\limits_{i = 1}^{K}\left( {1 - {p_{fail}\left( f_{i} \right)}} \right)^{u_{i}}} \right)}}}} & (13)\end{matrix}$

As before, the higher order terms in the above equation can be ignoredsince the feature probabilities are expected to be much smaller thanone. With this approximation the escape probability becomes:

$\begin{matrix}{p_{escape} = {\left( {1 - {\sum\limits_{i = 1}^{K}\mspace{11mu} {n_{i}{p_{fail}\left( f_{i} \right)}}}} \right)\left( \frac{\sum\limits_{i = 1}^{K}{u_{i}{p_{fail}\left( f_{i} \right)}}}{1 - {\sum\limits_{i = 1}^{K}{u_{i}{p_{fail}\left( f_{i} \right)}}}} \right)}} & (14)\end{matrix}$

Note that the above calculations can be performed on a per feature basis(for example, the escape probability for each individual feature can becalculated in a similar fashion).

Typically, test escape rates are expressed as defects per million (DPM)numbers, which is the number defective die in one million die that passtesting. The escape probability determined by the above equation can beeasily converted to this number by multiplying by 10⁶. Hence, estimationof the DPM number constitutes another use of feature fail probabilitiesestimated from volume diagnosis results that can be captured andreported by embodiments of the disclosed technology.

5. Alternative Procedures for Pareto Chart Calculation

In this section, alternative procedures for pareto chart calculation arediscussed. As discussed above, one major source of ambiguities indiagnosis comes from equivalent faults, whose corresponding defects canform a so-called “equivalent class.” A set of defects form an equivalentclass if their corresponding faults share the same signature and cannotbe distinguished without additional information. If the equivalent classconsists of defects from different classes, the diagnostic procedure maybe unable to identify the real failing mechanism. To simplifydiscussion, the equivalent classes will be used hereafter to refer todefects that have elements from different classes.

5.1 Error Estimation

Let C_(t)={C_(t1), C_(t2), . . . , C_(tk)} denote an equivalent classwhere C_(t1) represents the number of defects in the l-th class. If suchan equivalent class C_(t) is encountered in the defect identificationprocedure (21.1) and if it remains unresolved after incrementalsimulation (21.2) and diagnosis (21.3), without knowing which defectclass is the real cause, the diagnosis procedure will typically have toassign probabilistic credits to each class involved in C_(t). Assumingeach defect in C_(t) is equally likely to occur, the credits assignedcan be related to the number of defects in the class. For example:

$\left\{ {\frac{C_{t\; 1}}{\sum\limits_{l}C_{t\; l}},\frac{C_{t\; 2}}{\sum\limits_{l}C_{t\; l}},\ldots \mspace{14mu},\frac{C_{tk}}{\sum\limits_{l}C_{t\; l}}} \right\}.$

Let

_(i) denote the set of the equivalent classes that contain defects ofclass i. Let N be the total number of defective circuits being diagnosedLet N_(i-u) be the number of defective circuits that can be preciselydiagnosed as having class i defects. Therefore, the number of circuitswith defect class i is in the range [N_(i-u), N_(i-u)+|

_(i)|]. In the worst case, the error of diagnosed result for class i is|

_(i)|. Therefore, the ambiguity of the predicted pareto chart for kclasses can be measured with the average

∑ i    i  / k .

5.2 Data Calibration

The predicted distribution of yield loss mechanisms are desirablycalibrated such that, in the statistical sense, the estimation errorcaused by equivalent classes can be reduced. As shown in FIG. 32, datacalibration (22.2) can be performed in an iterative fashion withdiagnostic results computation (22.1).

In one exemplary embodiment, data calibration is based on the concept ofset probability. For example, let P(D=i) (i=1, 2, . . . ) be theprobability that defect class i occurs; let P(O=i) (i=1, 2, . . . ) bethe probability that the defect is predicted by diagnosis as class i;let P(O=i|D=j) (i,j=1, 2, . . . ) be the conditional probability thatthe defect is predicted as class i under the condition that defect classj occurs. Based on the probabilistic theory, the equation holds that:

$\begin{matrix}{{P\left( O_{i} \right)} = {\sum\limits_{j}^{\;}\; {{P\left( {O_{i}D_{j}} \right)}{P\left( D_{j} \right)}}}} & (15)\end{matrix}$

Let P(O) be the vector {P(O₁), P(O₂), . . . , P(O_(k))}, let P(D) be thevector {P(D₁), P(D)₂), . . . , P(D_(k))}. The formula relating P(O) andP(D) is then:

P ^(T)(O)=Γ×P ^(T)(D)  (16)

where Γ is a matrix with P(O_(i)|D_(j)) being an element on i-th row andj-th column.

As can be observed, P(O) is the pareto chart obtained through diagnosis.In the ideal case, there is no ambiguity between different classes, andP(O_(i)|D_(jk))=0 (i≠j). The conditional probability matrix r will beunit matrix, and P(O) will match P(D). If there is ambiguity, P(O) canbe calibrated by:

{tilde over (P)} ^(T)(O)=Γ⁻¹ ×P ^(T)(O).  (17)

The conditional probability can be estimated based on the informationcollected during the defect identification procedure (21.1). During anexemplar two-step procedure, the equivalent classes that have beenencountered can be recorded. The record for the equivalent class C, canbe a tuple {L_(t), C_(t)} where L_(t) represents the number ofoccurrences of C_(t) during identification stages.

Suppose the pareto chart P(O) is {P(O₁)=n₁, P(O₂)=n₂, . . . . ,P(O_(k))=n_(k)} after N defective parts were diagnosed. The conditionalprobability P(O_(i)|D_(j)) can be estimated using equation:

$\begin{matrix}{\; {{{P\left( {O_{i}D_{j}} \right)} = {\frac{P\left( {O_{i},D_{j}} \right)}{P\left( D_{j} \right)}\mspace{56mu} = {\frac{N\left( {O_{i},D_{j}} \right)}{N\left( D_{j} \right)} \approx \frac{N\left( {O_{i},D_{j}} \right)}{N \cdot n_{j}}}}},}} & (18)\end{matrix}$

where N(O_(i), D_(j)) are those defects of class j that are diagnosed asof class i. It can be estimated from the set of the equivalent classes

_(i)∩

_(j). Consider an equivalent class C_(t)ε

_(i)∩

_(j). The equivalent class C_(t) contains indistinguishable defects ofclass i and J. Let C_(t) be { . . . , C_(th) . . . , C_(tf), . . . }. Asdescribed above, the probability that a defect in C_(t) is diagnosed asof class i is

$C_{ti}/{\sum\limits_{i}^{\;}\; {C_{ti}.}}$

Assume P(O) (P(O)={n₁, n₂, . . . , n_(k)}) matches P(D) closely, andassume that the same distribution P(D) also applies to the set ofdefects that are considered by the diagnosis to be in the equivalentclass C_(t). Therefore, out of T occurrences of C_(t), the number ofcircuits with defects of class j can be calculated as

${{Tn}_{j}/{\sum\limits_{i}^{\;}\; n_{i}}},$

and the number of times that defects of class j are predicted as ofclass i can calculated as

$T\frac{C_{ti}}{\sum\limits_{i}^{\;}C_{\text{?}}}{\frac{n_{j}}{\sum\limits_{i}^{\;}n_{i}}.\text{?}}\text{indicates text missing or illegible when filed}$

In other words, for each occurrence of C_(i), the probability thatdefects of class j are predicted as of class i is

$\mspace{11mu} {\frac{C_{\text{?}}}{\sum\limits_{i}\; C_{\text{?}}}{\frac{n_{j}}{\sum\limits_{i}n_{i}}.\text{?}}\text{indicates text missing or illegible when filed}}$

Consider all the equivalent classes in

_(i)∩

_(j), and suppose |

_(i)∩

_(j)|=m, then N(O_(b) D_(j)) can be computed as:

$\begin{matrix}{{N\left( {O_{i},D_{j}} \right)} = {\sum\limits_{t = 1}^{\text{?}}\; {{\left( {\frac{C_{ti}}{\sum\limits_{i}\; C_{ti}}\frac{n_{j}}{\sum\limits_{i}n_{i}}} \right).\text{?}}\text{indicates text missing or illegible when filed}}}} & (19)\end{matrix}$

{tilde over (P)}(O) can now be computed by combining equations (17),(18), and (19).

The calibration iterates by recomputing the conditional probabilitymatrix Γ with the calibrated {tilde over (P)}(O). The iteration stopsafter a certain number of cycles, or the error between {tilde over(P)}(O) of consecutive runs is less than the predetermined threshold.

Analysis of Miscellaneous Defects and Learning of New Defect Rules

Miscellaneous defects are those that cannot be identified as belongingto any classes that have been defined previously. The data produced bythe incremental simulation (21.2) and incremental diagnostic (21.3)procedures can indicate the existence of defects that are not properlymodeled and/or defects that are not considered during the faultsimulation and fault dictionary computation stage. When requested, ananalysis procedure can be activated to process the data and extract thestatistical information. An advanced diagnoses component (such asadvanced diagnosis component (4726) in FIG. 47) can use the statisticalinformation to simulate the defects and to update the fault dictionary.If certain criteria are met, new defect rules can be generated andapplied during the next iteration of the defect extraction process.

The diagnosis component can be made self-adaptive, for example, in anyone or more of the following ways.

1. Some newly identified defects are highly likely to occur. Theirfailing responses are desirably recorded in the fault dictionary. Theircorresponding faults can be simulated with the same test set as was usedpreviously during the fault dictionary computation stage. The faultdictionary can be updated with the simulated failing responses. Todetermine the likelihood of occurrence of a defect, the number of timesthe defect is encountered can be counted.

2. From the incremental diagnostic results (21.3), it can be observedthat a new fault type is more effective in describing the observedfailing behaviors than the ones used previously. If this is true for asignificant percentage of defects, the newly identified defects, as wellas the defects previously stored in the fault dictionary if necessary,can be simulated under the new fault type. The fault dictionary can beupdated with the simulated failing responses.

3. If miscellaneous defects with certain characteristics that were notconsidered previously are found to be highly likely to occur, the newlyidentified defect-inducing characteristics are desirably incorporatedinto the defect rule set and a new defect class defined in a defectextraction rule update procedure (26). The defect extraction (7) can beperformed on the layout using the new rules. For the newly extracteddefects, the corresponding faults can be simulated with the same testset as was used previously during the fault dictionary computationstage. The fault dictionary can be updated with the simulated failingresponses.

These self-leaning, adaptive procedures can be initiated on a regularbasis, or at the user's request.

Update of Defect Ranking (24)

As discussed above, defect rankings are initially determined by theprobabilistic measures related to layout features and manufacturingprocess parameters. According to one exemplary embodiment of the generalmethod, the number of occurrences for each defect class is countedduring the test-result data post-processing procedure so that defectrankings can be dynamically updated with the relative frequency ofoccurrence.

Special Considerations for On-chip Compression Logic

For integrated circuits that use on-chip compression logic such asoutput response compactors, some special considerations arise. Forexample, one consideration is the limited possibility for diagnosis.Different compactors have different capabilities, but someimplementations offer diagnosis quality that is comparable to integratedcircuit without compactors, e.g., G. Mrugalski, J. Rajski, C. Wang, A.Pogiel, J. Tyszer, “Fault Diagnosis in Designs with ConvolutionalCompactors,” ITC 2004, pp. 498-507. Another consideration is that thecompactor can invalidate, the differentiation of candidate defects bythe compression method of the compactor. As an example, consider FIGS.28 through 30. FIG. 28 shows the case without an output responsecompactor. Fault effects can be observed at a number of scan cells in afirst scan chain (2801) and a second chain (2802), thus the defects aredistinguishable. However, as shown in FIG. 29, with an output responsecompactor (2901), the effects of the defects may no longer bedistinguishable because, for example, the output responses for bothdefects cancel each other out (in the case of a two-defect assumption).Another possibility, for example, is that the observable output responsefor both defects is made identical by the compactor. For both cases, thearchitecture shown in FIG. 30 offers one possible solution that adds acomponent to the output response compactor (2901). This component,termed the “defect resolution output response selector” (3001) enablesthe ATPG to manipulate by a control signal on control line (3002) thenormal operation of the output response compactor (2901) in order toretain the distinguishing capability of the computed candidate testpattern. There are a number of possible ways to implement and use theselector circuit (3001) exemplified in FIG. 30. For example, disablingcertain scan chains from compaction during testing, or rerouting certainscan chain outputs to different inputs of the compactor during testing.In particular exemplary embodiments, the defect resolution outputresponse selector (3001) adds a stage to the output response compactor(2901) and is configured to manipulate the output response compactor(2901) to make the output response compactor (2901) compute differentsignatures for the otherwise indistinguishable faults.

Other Usage Scenarios

The exemplary methods, apparatus, and system described in thisembodiment assume that the design and test generation, production andproduction test are performed by the same entity or that the informationexchange between different entities is unrestricted. In the following,however, a usage scenario for an exemplary embodiment of the disclosedtechnology is described wherein the information exchange is restricted.

For example, each step is owned by a different entity, which wants toexchange only the absolute minimum of information. The design entityowns the layout data, the netlist, and is the only one who can generatetest patterns and is not willing to share the netlist. The second entityis the producer, who receives only the layout data, and whose goal ishigh yield. It may not share rules, which might increase its yield, orgive up secrets of the production. Only the necessary DFM rules aredisclosed to the design entity. Finally, there is the production-testentity, which knows nothing about the integrated circuit. It receivesonly the test patterns and the produced die. With a few modifications tothe exemplary procedure described above, substantially the same DFM andyield improvements are possible in this environment. For example, onesolution uses symbolic extraction rules provided by the producer throughspecial (encoded) DFM rules for the design entity, which are meant to beused in the ATPG, for example, to increase the defect resolution. Acorresponding symbolic dictionary (or thesaurus) can be generated by thedesign entity. Symbolic in this context means that the actual defect,defect extraction rule, and DFM rule do not reveal any knowledgeconcerning the design or the production line. For sake of this example,assume that the defects are simply enumerated. Both the design entityand the production entity may compute the same defect list based on thelayout data and the DFM rules. The design entity may use the defect listto generate test patterns, and the production entity may receivediagnosis analysis results based on the symbolic dictionary. Theproduction entity in turn can analyze the problem completely and cantake corrective steps. If required, the production entity sends improved(encoded) DFM rules for the ATPG to the design entity and requestsadditional test patterns.

Exemplary Computing Environments

Any of the aspects of the technology described above may be performedusing a distributed computer network. FIG. 48 shows one such exemplarynetwork. A server computer (4800) can have an associated storage device(4802) (internal or external to the server computer). For example, theserver computer (4800) can be configured to generate or update DFM rulesor defect extraction rules, to generate test patterns, test responses,or fault dictionaries, to diagnose faults or defects from test results,or compute yield analysis statistics and graphical representationsthereof according to any of the embodiments described above (forexample, as part of an EDA software tool). The server computer (4800)may be coupled to a network, shown generally at (4804), which cancomprise, for example, a wide-area network, a local-area network, aclient-server network, the Internet, or other such network. One or moreclient computers, such as those shown at (4806), (4808) may be coupledto the network (4804) using a network protocol. The work may also beperformed on a single, dedicated workstation, which has its own memoryand one or more CPUs.

FIG. 49 shows another exemplary network One or more computers (4902)communicate via a network (4904) and form a computing environment (4900)(for example, a distributed computing environment). Each of thecomputers (4902) in the computing environment (4900) can be used toperform at least a portion of a test response generation processaccording to, for example, any of the embodiments described above (forexample, as part of an EDA software tool, such as an ATPG tool). Forinstance, each of the computers may perform test pattern andtest-response generation for different portions of the circuit design,for different types of patterns, or according to various other criteria.The network (4904) in the illustrated embodiment is also coupled to oneor more client computers.

FIG. 50 shows one nonlimiting example of using the computingenvironments illustrated in FIGS. 48 and 49. In particular, FIG. 50shows that a database or data structure containing design information(for example, a netlist) and a database or data structure containingextracted defect data (for example, from fault/defect extractioncomponent (4710)) can be analyzed using a remote server computer (suchas the server computer (4800) shown in FIG. 48) or remote computingenvironment (such as the computing environment (4900) shown in FIG. 49)in order to generate test data for the design, including test patternsand test responses, using embodiments of the disclosed technology. At(5002), for example, the client computer sends design and extracteddefect data to the remote server or computing environment. At (5002),the design and extracted defect data are received and loaded by theremote server or by respective components of the computing environment.At (5006), test data is created, including test patterns, testresponses, and a fault dictionary using any of the disclosedembodiments. At (5008), the remote server or computing environment sendsthe test data (including the test patterns, test responses, and faultdictionary) to the client computer, which receives the test data at(5010). It should be apparent to those skilled in the art that theexample shown in FIG. 50 is not the only way to generate test data usingmultiple computers. For instance, the design and extracted defect datacan be stored on tangible computer-readable media that are not on anetwork and that are sent separately to the server or computingenvironment (for example, one or more CD-ROMs, DVDs, or portable harddrives). Or, the server or remote computing environment may perform onlya portion of the test pattern generation procedures.

Having illustrated and described the principles of the illustratedembodiments, it will be apparent to those skilled in the art that theembodiments can be modified in arrangement and detail without departingfrom such principles. In view of the many possible embodiments, it willbe recognized that the illustrated embodiments include only examples andshould not be taken as a limitation on the scope of the invention.

1.-44. (canceled)
 45. A computer-implemented method, comprising:receiving information indicative of integrated circuit failures observedduring testing of multiple integrated circuits and potential defectsthat may have caused the integrated circuit failures, the potentialdefects having been extracted and targeted for testing using extractionrules derived from design manufacturing rules; analyzing the informationto determine one or more failure rates associated with one or more ofthe potential defects; and reporting the determined failure rates. 46.The method of claim 45, wherein the information received comprises oneor more of the following: (a) diagnosis results; (b) one or more listsof the potential defects; or (c) information about detection of thepotential defects during the testing.
 47. The method of claim 45,further comprising determining an estimate of the yield of theintegrated circuits based at least in part on the determined failurerates.
 48. The method of claim 45, wherein the integrated circuitscomprise a first set of integrated circuits, the method furthercomprising determining an estimate of the yield of a second set ofintegrated circuits based at least in part on the determined failurerates.
 49. The method of claim 45, further comprising determining anestimate of the escape rate of a respective potential defect or of theintegrated circuits based at least in part on the determined failurerates.
 50. The method of claim 45, wherein the integrated circuitscomprise a first set of integrated circuits, the method furthercomprising determining an estimate of the escape rate of a potentialdefect of a second set of integrated circuits or of the second set ofintegrated circuits based at least in part on the determined failurerates.
 51. The method of claim 45, further comprising estimating a yieldsensitivity curve for at least one of the design manufacturing rulesbased at least in part on the determined failure rates.
 52. The methodof claim 45 performed repetitively over time, the method furthercomprising determining production trends based on changes in thedetermined probabilities observed over time.
 53. The method of claim 45,further comprising performing one or more of the following based atleast in part on the reported probabilities: (a) adjusting one or moredesign manufacturing rules; (b) adjusting one or more defect extractionrules; or (c) providing recommended modifications for one or morefeatures in the integrated circuits.
 54. The method of claim 53, whereinone or more features in the integrated circuits are modified based atleast in part on the reported probabilities, the method furthercomprising producing one or more integrated circuits having the modifiedone or more features.
 55. The method of claim 45, the diagnostic resultsare obtained through application of at least one fault dictionary. 56.The method of claim 55, wherein the at least one fault dictionarycomprises a compressed fault dictionary that uses one or more bit masksto identify potential defects.
 57. The method of claim 45, wherein theanalyzing comprises: constructing probability models associated with thefeature fail rates; relating the constructed probability models to thediagnostic results received; and computing estimated feature fail ratesusing regression analysis.
 58. One or more tangible computer-readablemedia storing computer-executable instructions for causing a computer toperform a method, the method comprising: receiving informationindicative of integrated circuit failures observed during testing ofmultiple integrated circuits and potential defects that may have causedthe integrated circuit failures, the potential defects having beenextracted and targeted for testing using extraction rules derived fromdesign manufacturing rules; analyzing the information to determine oneor more failure rates associated with one or more of the potentialdefects; and reporting the determined failure rates.
 59. At least onecomputer programmed to carry out a method, the method comprising:receiving information indicative of integrated circuit failures observedduring testing of multiple integrated circuits and potential defectsthat may have caused the integrated circuit failures, the potentialdefects having been extracted and targeted for testing using extractionrules derived from design manufacturing rules: analyzing the informationto determine one or more failure rates associated with one or more ofthe potential defects; and reporting the determined failure rates. 60.The one or more tangible computer-readable media of claim 58, whereinthe information received comprises one or more of the following: (a)diagnosis results; (b) one or more lists of the potential defects; or(c) information about detection of the potential defects during thetesting.
 61. The one or more tangible computer-readable media of claim58, wherein the method further comprises determining an estimate of theyield of the integrated circuits based at least in part on thedetermined failure rates.
 62. The one or more tangible computer-readablemedia of claim 58, wherein the integrated circuits comprise a first setof integrated circuits, and the method further comprises determining anestimate of the yield of a second set of integrated circuits based atleast in part on the determined failure rates.
 63. The one or moretangible computer-readable media of claim 58, wherein the method furthercomprises determining an estimate of the escape rate of a respectivepotential defect or of the integrated circuits based at least in part onthe determined failure rates.
 64. The one or more tangiblecomputer-readable media of claim 58, wherein the integrated circuitscomprise a first set of integrated circuits, and wherein the methodfurther comprises determining an estimate of the escape rate of apotential defect of a second set of integrated circuits or of the secondset of integrated circuits based at least in part on the determinedfailure rates.
 65. The one or more tangible computer-readable media ofclaim 58, wherein the method further comprises estimating a yieldsensitivity curve for at least one of the design manufacturing rulesbased at least in part on the determined failure rates.
 66. The one ormore tangible computer-readable media of claim 58, wherein the method isperformed repetitively over time, and the method further comprisesdetermining production trends based on changes in the determinedprobabilities observed over time.
 67. The one or more tangiblecomputer-readable media of claim 58, wherein the method furthercomprises performing one or more of the following based at least in parton the reported probabilities: (a) adjusting one or more designmanufacturing rules; (b) adjusting one or more defect extraction rules;or (c) providing recommended modifications for one or more features inthe integrated circuits.
 68. The one or more tangible computer-readablemedia of claim 58, wherein the diagnostic results are obtained throughapplication of at least one fault dictionary.
 69. The one or moretangible computer-readable media of claim 68, wherein the at least onefault dictionary comprises a compressed fault dictionary that uses oneor more bit masks to identify potential defects.
 70. The one or moretangible computer-readable media of claim 58, wherein the analyzingcomprises: constructing probability models associated with the featurefail rates; relating the constructed probability models to thediagnostic results received; and computing estimated feature fail ratesusing regression analysis.